disp123456.vhd

来自「张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DISP123456 IS
    PORT(
        CLK       : IN        STD_LOGIC;
        SEG7   : OUT    STD_LOGIC_VECTOR(7 DOWNTO 0);
        CTRL   : OUT    STD_LOGIC_VECTOR(5 DOWNTO 0)
        );
END DISP123456;
ARCHITECTURE DISPLAY OF DISP123456 IS
COMPONENT DISP
    PORT(
        DIN    : IN    STD_LOGIC_VECTOR(2 DOWNTO 0);
        SEG7: OUT    STD_LOGIC_VECTOR(7 DOWNTO 0));
    END COMPONENT;
COMPONENT CNT3B
    PORT (CLK : IN  STD_LOGIC;
            Q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
    END COMPONENT;
COMPONENT SW
    PORT(
        SW    : IN    STD_LOGIC_VECTOR(2 DOWNTO 0);
        CTRL: OUT    STD_LOGIC_VECTOR(5 DOWNTO 0));
    END COMPONENT;

SIGNAL IO : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
U1 : CNT3B PORT MAP (CLK => CLK , Q => IO);
U2 : DISP PORT MAP (SEG7 => SEG7 , DIN => IO);
U3 : SW PORT MAP (SW => IO , CTRL => CTRL);
END DISPLAY;