test_bcd8.vhdtst

来自「张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘」· VHDTST 代码 · 共 106 行

------------------------------------------------------------
-- VHDL Testbench for BCD8
-- 2003 6 5 1 19 17
-- Created by "EditVHDL"
-- "Copyright (c) 2002 Altium Limited"
------------------------------------------------------------

Library IEEE;
Use     IEEE.std_logic_1164.all;
Use     IEEE.std_logic_textio.all;
Use     STD.textio.all;
------------------------------------------------------------

------------------------------------------------------------
entity TestBCD8 is
end TestBCD8;
------------------------------------------------------------

------------------------------------------------------------
architecture stimulus of TestBCD8 is
    file RESULTS: TEXT open WRITE_MODE is "results.txt";
    procedure WRITE_RESULTS(
        CLEAR: std_logic;
        CLOCK: std_logic;
        ENABLE: std_logic;
        LOWER: std_logic_vector(3 downto 0);
        PARITY: std_logic;
        UPPER: std_logic_vector(3 downto 0);
        URCO: std_logic
    ) is
        variable l_out : line;
    begin
        write(l_out, now, right, 15);
        write(l_out, CLEAR, right, 2);
        write(l_out, CLOCK, right, 2);
        write(l_out, ENABLE, right, 2);
        write(l_out, LOWER, right, 5);
        write(l_out, PARITY, right, 2);
        write(l_out, UPPER, right, 5);
        write(l_out, URCO, right, 2);
        writeline(RESULTS, l_out);
    end procedure;

    component BCD8
        port (
            CLEAR: in std_logic;
            CLOCK: in std_logic;
            ENABLE: in std_logic;
            LOWER: out std_logic_vector(3 downto 0);
            PARITY: out std_logic;
            UPPER: out std_logic_vector(3 downto 0);
            URCO: out std_logic
        );
    end component;

    signal CLEAR: std_logic;
    signal CLOCK: std_logic;
    signal ENABLE: std_logic;
    signal LOWER: std_logic_vector(3 downto 0);
    signal PARITY: std_logic;
    signal UPPER: std_logic_vector(3 downto 0);
    signal URCO: std_logic;

begin
    DUT:BCD8 port map (
        CLEAR => CLEAR,
        CLOCK => CLOCK,
        ENABLE => ENABLE,
        LOWER => LOWER,
        PARITY => PARITY,
        UPPER => UPPER,
        URCO => URCO
    );

    STIMULUS0:process
    begin
        -- insert stimulus here
        ENABLE <= '1';
        CLEAR  <= '1';
        wait for 1 ns;
        CLEAR <= '0';
        wait;
    end process;

    CLK0:process
    begin
       CLOCK <= '1';
       wait for 10 ns;
       CLOCK <= '0';
       wait for 10 ns;
    end process;

    WRITE_RESULTS(
        CLEAR,
        CLOCK,
        ENABLE,
        LOWER,
        PARITY,
        UPPER,
        URCO
    );

end architecture;
------------------------------------------------------------

------------------------------------------------------------