📄 main.lis
字号:
06EA 4E80 ldd R4,y+6
06EC 5F80 ldd R5,y+7
06EE 2882 std y+0,R2
06F0 3982 std y+1,R3
06F2 4A82 std y+2,R4
06F4 5B82 std y+3,R5
06F6 L52:
06F6 .dbline 235
06F6 L53:
06F6 .dbline 235
06F6 20909B00 lds R2,155
06FA 25FE sbrs R2,5
06FC FCCF rjmp L52
06FE X36:
06FE .dbline 235
06FE 8BE2 ldi R24,43
0700 80939C00 sts 156,R24
0704 .dbline 235
0704 L55:
0704 .dbline 236
0704 ; while(!(UCSR1A&(1<<UDRE1)));
0704 L56:
0704 .dbline 236
0704 20909B00 lds R2,155
0708 25FE sbrs R2,5
070A FCCF rjmp L55
070C X37:
070C .dbline 237
070C ; UDR1=(n/10000)%10+48;
070C 80E1 ldi R24,16
070E 97E2 ldi R25,39
0710 A0E0 ldi R26,0
0712 B0E0 ldi R27,0
0714 0881 ldd R16,y+0
0716 1981 ldd R17,y+1
0718 2A81 ldd R18,y+2
071A 3B81 ldd R19,y+3
071C BA93 st -y,R27
071E AA93 st -y,R26
0720 9A93 st -y,R25
0722 8A93 st -y,R24
0724 0E940000 xcall div32s
0728 8AE0 ldi R24,10
072A 90E0 ldi R25,0
072C A0E0 ldi R26,0
072E B0E0 ldi R27,0
0730 BA93 st -y,R27
0732 AA93 st -y,R26
0734 9A93 st -y,R25
0736 8A93 st -y,R24
0738 0E940000 xcall mod32s
073C 1801 movw R2,R16
073E 2901 movw R4,R18
0740 80E3 ldi R24,48
0742 90E0 ldi R25,0
0744 A0E0 ldi R26,0
0746 B0E0 ldi R27,0
0748 280E add R2,R24
074A 391E adc R3,R25
074C 4A1E adc R4,R26
074E 5B1E adc R5,R27
0750 20929C00 sts 156,R2
0754 L58:
0754 .dbline 238
0754 ; while(!(UCSR1A&(1<<UDRE1)));
0754 L59:
0754 .dbline 238
0754 20909B00 lds R2,155
0758 25FE sbrs R2,5
075A FCCF rjmp L58
075C X38:
075C .dbline 239
075C ; UDR1=(n/1000)%10+48;
075C 88EE ldi R24,232
075E 93E0 ldi R25,3
0760 A0E0 ldi R26,0
0762 B0E0 ldi R27,0
0764 0881 ldd R16,y+0
0766 1981 ldd R17,y+1
0768 2A81 ldd R18,y+2
076A 3B81 ldd R19,y+3
076C BA93 st -y,R27
076E AA93 st -y,R26
0770 9A93 st -y,R25
0772 8A93 st -y,R24
0774 0E940000 xcall div32s
0778 8AE0 ldi R24,10
077A 90E0 ldi R25,0
077C A0E0 ldi R26,0
077E B0E0 ldi R27,0
0780 BA93 st -y,R27
0782 AA93 st -y,R26
0784 9A93 st -y,R25
0786 8A93 st -y,R24
0788 0E940000 xcall mod32s
078C 1801 movw R2,R16
078E 2901 movw R4,R18
0790 80E3 ldi R24,48
0792 90E0 ldi R25,0
0794 A0E0 ldi R26,0
0796 B0E0 ldi R27,0
0798 280E add R2,R24
079A 391E adc R3,R25
079C 4A1E adc R4,R26
079E 5B1E adc R5,R27
07A0 20929C00 sts 156,R2
07A4 L61:
07A4 .dbline 240
07A4 ; while(!(UCSR1A&(1<<UDRE1)));
07A4 L62:
07A4 .dbline 240
07A4 20909B00 lds R2,155
07A8 25FE sbrs R2,5
07AA FCCF rjmp L61
07AC X39:
07AC .dbline 241
07AC ; UDR1=(n/100)%10+48;
07AC 84E6 ldi R24,100
07AE 90E0 ldi R25,0
07B0 A0E0 ldi R26,0
07B2 B0E0 ldi R27,0
07B4 0881 ldd R16,y+0
07B6 1981 ldd R17,y+1
07B8 2A81 ldd R18,y+2
07BA 3B81 ldd R19,y+3
07BC BA93 st -y,R27
07BE AA93 st -y,R26
07C0 9A93 st -y,R25
07C2 8A93 st -y,R24
07C4 0E940000 xcall div32s
07C8 8AE0 ldi R24,10
07CA 90E0 ldi R25,0
07CC A0E0 ldi R26,0
07CE B0E0 ldi R27,0
07D0 BA93 st -y,R27
07D2 AA93 st -y,R26
07D4 9A93 st -y,R25
07D6 8A93 st -y,R24
07D8 0E940000 xcall mod32s
07DC 1801 movw R2,R16
07DE 2901 movw R4,R18
07E0 80E3 ldi R24,48
07E2 90E0 ldi R25,0
07E4 A0E0 ldi R26,0
07E6 B0E0 ldi R27,0
07E8 280E add R2,R24
07EA 391E adc R3,R25
07EC 4A1E adc R4,R26
07EE 5B1E adc R5,R27
07F0 20929C00 sts 156,R2
07F4 L64:
07F4 .dbline 242
07F4 ; while(!(UCSR1A&(1<<UDRE1)));
07F4 L65:
07F4 .dbline 242
07F4 20909B00 lds R2,155
07F8 25FE sbrs R2,5
07FA FCCF rjmp L64
07FC X40:
07FC .dbline 243
07FC ; UDR1=(n/10)%10+48;
07FC 8AE0 ldi R24,10
07FE 90E0 ldi R25,0
0800 A0E0 ldi R26,0
0802 B0E0 ldi R27,0
0804 0881 ldd R16,y+0
0806 1981 ldd R17,y+1
0808 2A81 ldd R18,y+2
080A 3B81 ldd R19,y+3
080C BA93 st -y,R27
080E AA93 st -y,R26
0810 9A93 st -y,R25
0812 8A93 st -y,R24
0814 0E940000 xcall div32s
0818 8AE0 ldi R24,10
081A 90E0 ldi R25,0
081C A0E0 ldi R26,0
081E B0E0 ldi R27,0
0820 BA93 st -y,R27
0822 AA93 st -y,R26
0824 9A93 st -y,R25
0826 8A93 st -y,R24
0828 0E940000 xcall mod32s
082C 1801 movw R2,R16
082E 2901 movw R4,R18
0830 80E3 ldi R24,48
0832 90E0 ldi R25,0
0834 A0E0 ldi R26,0
0836 B0E0 ldi R27,0
0838 280E add R2,R24
083A 391E adc R3,R25
083C 4A1E adc R4,R26
083E 5B1E adc R5,R27
0840 20929C00 sts 156,R2
0844 L67:
0844 .dbline 244
0844 ; while(!(UCSR1A&(1<<UDRE1)));
0844 L68:
0844 .dbline 244
0844 20909B00 lds R2,155
0848 25FE sbrs R2,5
084A FCCF rjmp L67
084C X41:
084C .dbline 245
084C ; UDR1=n%10+48;
084C 8AE0 ldi R24,10
084E 90E0 ldi R25,0
0850 A0E0 ldi R26,0
0852 B0E0 ldi R27,0
0854 0881 ldd R16,y+0
0856 1981 ldd R17,y+1
0858 2A81 ldd R18,y+2
085A 3B81 ldd R19,y+3
085C BA93 st -y,R27
085E AA93 st -y,R26
0860 9A93 st -y,R25
0862 8A93 st -y,R24
0864 0E940000 xcall mod32s
0868 1801 movw R2,R16
086A 2901 movw R4,R18
086C 80E3 ldi R24,48
086E 90E0 ldi R25,0
0870 A0E0 ldi R26,0
0872 B0E0 ldi R27,0
0874 280E add R2,R24
0876 391E adc R3,R25
0878 4A1E adc R4,R26
087A 5B1E adc R5,R27
087C 20929C00 sts 156,R2
0880 .dbline 246
0880 ; if (huanhang)
0880 0884 ldd R0,y+8
0882 0020 tst R0
0884 79F0 breq L79
0886 X42:
0886 .dbline 247
0886 ; {
0886 L72:
0886 .dbline 248
0886 ; while(!(UCSR1A&(1<<UDRE1)));
0886 L73:
0886 .dbline 248
0886 20909B00 lds R2,155
088A 25FE sbrs R2,5
088C FCCF rjmp L72
088E X43:
088E .dbline 249
088E ; UDR1=0x0d;
088E 8DE0 ldi R24,13
0890 80939C00 sts 156,R24
0894 L75:
0894 .dbline 250
0894 ; while(!(UCSR1A&(1<<UDRE1)));
0894 L76:
0894 .dbline 250
0894 20909B00 lds R2,155
0898 25FE sbrs R2,5
089A FCCF rjmp L75
089C X44:
089C .dbline 251
089C ; UDR1=0x0a;
089C 8AE0 ldi R24,10
089E 80939C00 sts 156,R24
08A2 .dbline 252
08A2 ; }
08A2 0EC0 xjmp L71
08A4 L78:
08A4 .dbline 255
08A4 ; else
08A4 ; {
08A4 ; while(!(UCSR1A&(1<<UDRE1)));
08A4 L79:
08A4 .dbline 255
08A4 20909B00 lds R2,155
08A8 25FE sbrs R2,5
08AA FCCF rjmp L78
08AC X45:
08AC .dbline 256
08AC ; UDR1=0x20;
08AC 80E2 ldi R24,32
08AE 80939C00 sts 156,R24
08B2 L81:
08B2 .dbline 257
08B2 ; while(!(UCSR1A&(1<<UDRE1)));
08B2 L82:
08B2 .dbline 257
08B2 20909B00 lds R2,155
08B6 25FE sbrs R2,5
08B8 FCCF rjmp L81
08BA X46:
08BA .dbline 258
08BA ; UDR1=0x20;
08BA 80E2 ldi R24,32
08BC 80939C00 sts 156,R24
08C0 .dbline 259
08C0 ; }
08C0 L71:
08C0 .dbline -2
08C0 L46:
08C0 .dbline 0 ; func end
08C0 2896 adiw R28,8
08C2 0895 ret
08C4 .dbsym l n 0 L
08C4 .dbsym l huanhang 8 c
08C4 .dbsym l NUM 4 L
08C4 .dbend
08C4 .dbfunc e timer0_init _timer0_init fV
.even
08C4 _timer0_init::
08C4 .dbline -1
08C4 .dbline 269
08C4 ; }
08C4 ;
08C4 ;
08C4 ;
08C4 ; //TIMER0 initialize - prescale:64
08C4 ; // WGM: PWM Fast
08C4 ; // desired value: 1KHz
08C4 ; // actual value: 0.488KHz (-104.8%)
08C4 ; void timer0_init(void)
08C4 ; {
08C4 .dbline 270
08C4 ; TCCR0 = 0x00; //stop
08C4 2224 clr R2
08C6 23BE out 0x33,R2
08C8 .dbline 271
08C8 ; ASSR = 0x00; //set async mode
08C8 20BE out 0x30,R2
08CA .dbline 272
08CA ; TCNT0 = 0x01; //set count
08CA 81E0 ldi R24,1
08CC 82BF out 0x32,R24
08CE .dbline 273
08CE ; OCR0 = 0x0f;
08CE 8FE0 ldi R24,15
08D0 81BF out 0x31,R24
08D2 .dbline 274
08D2 ; TCCR0 = 0x6C; //start timer
08D2 8CE6 ldi R24,108
08D4 83BF out 0x33,R24
08D6 .dbline -2
08D6 L84:
08D6 .dbline 0 ; func end
08D6 0895 ret
08D8 .dbe⌨️ 快捷键说明
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