📄 spislv.asm
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;****************************************************************************
; File Name : TMS320x240 SPI Slave Mode Example Code
;
; TMS320x240 SPI example code #2: 4 Pin SPI option
; - SLAVE MODE
; - Interrupts are enabled
; - # bytes of data transmitted - 7h
; - # bytes of data received - 8h
;
*****************************************************************************
; SET statements for '24x devices are device dependent. The SET locations
; used in this example are typically true for devices with only one SPI
; module. Consult the device data sheet to determine the exact memory map
; locations of the modules you will be accessing (control registers, RAM,
; ROM).
;
.include "f240regs.h" ; contains a list of SET statements
; for all registers on TMS320F240.
DP_PF1 .set 224 ; 1st Data Page of peripheral registers (7000h/80h)
; The following SET statements for the SPI are contained in f240regs.h
; and are shown explicitly for clarity.
;Serial Peripheral Interface (SPI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPICCR .set 07040h ; SPI Configuration Control Register
SPICTL .set 07041h ; SPI Operation Control Register
SPISTS .set 07042h ; SPI Status Register
SPIBRR .set 07044h ; SPI Baud Rate Register
SPIEMU .set 07046h ; SPI Emulation Buffer Register
SPIBUF .set 07047h ; SPI Serial Input Buffer Register
SPIDAT .set 07049h ; SPI Serial Data Register
SPIPC1 .set 0704Dh ; SPI Port Control Register #1
SPIPC2 .set 0704Eh ; SPI Port Control Register #2
SPIPRI .set 0704Fh ; SPI Priority Register
;-----------------------------------------------------------
; Constant definitions
;-----------------------------------------------------------
LENGTH .set 08h ; length of the data stream to be
; transmitted/received by SEND_ALL
DECODE .set 01h ; Decode value to used to enable slave
; transmissions.
;-----------------------------------------------------------
; Variable definitions
;-----------------------------------------------------------
;-----------------------------------------------------------
; The transmit and receive buffer locations are defined below.
; The actual .bss location will need to be defined in the
; linker control file.
;
.bss DATAOUT,LENGTH ; Location of LENGTH byte character stream
; transmitted by the SEND_ALL routine.
.bss DATAIN,LENGTH ; Location of LENGTH byte character stream
; received by the SEND_ALL routine.
;-----------------------------------------------------------
;-----------------------------------------------------------
; Macro definitions
;-----------------------------------------------------------
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;===========================================================
; Initialized data for SEND_ALL subroutine
;===========================================================
.data
TXDATA .word 0FDh,0FBh,0F7h,0EFh,0DFh,0BFh,07Fh
;===========================================================
; Reset & interrupt vectors
;===========================================================
.sect "vectors"
RSVECT B START ; PM 0 Reset Vector 1
INT1 B INT1_ISR ; PM 2 Int level 1 4
INT2 B PHANTOM ; PM 4 Int level 2 5
INT3 B PHANTOM ; PM 6 Int level 3 6
INT4 B PHANTOM ; PM 8 Int level 4 7
INT5 B INT1_ISR ; PM A Int level 5 8
INT6 B PHANTOM ; PM C Int level 6 9
RESERVED B PHANTOM ; PM E (Analysis Int) 10
SW_INT8 B PHANTOM ; PM 10 User S/W int -
SW_INT9 B PHANTOM ; PM 12 User S/W int -
SW_INT10 B PHANTOM ; PM 14 User S/W int -
SW_INT11 B PHANTOM ; PM 16 User S/W int -
SW_INT12 B PHANTOM ; PM 18 User S/W int -
SW_INT13 B PHANTOM ; PM 1A User S/W int -
SW_INT14 B PHANTOM ; PM 1C User S/W int -
SW_INT15 B PHANTOM ; PM 1E User S/W int -
SW_INT16 B PHANTOM ; PM 20 User S/W int -
TRAP B PHANTOM ; PM 22 Trap vector -
NMI B PHANTOM ; PM 24 Non maskable Int 3
EMU_TRAP B PHANTOM ; PM 26 Emulator Trap 2
SW_INT20 B PHANTOM ; PM 28 User S/W int -
SW_INT21 B PHANTOM ; PM 2A User S/W int -
SW_INT22 B PHANTOM ; PM 2C User S/W int -
SW_INT23 B PHANTOM ; PM 2E User S/W int -
; Begin the Reset initialization here ...
.text
START:
CLRC SXM ; Clear Sign Extension Mode
CLRC OVM ; Reset Overflow Mode
* Set Data Page pointer to page 1 of the peripheral frame
LDP #DP_PF1 ; Page DP_PF1 includes WET through EINT frames
* initialize WDT registers
SPLK #06Fh, WDCR ; clear WDFLAG, Disable WDT, set WDT for 1 second
; overflow (max)
SPLK #07h, RTICR ; clear RTI Flag, set RTI for 1 second
; overflow (max)
* EVM 10MHz oscillator settings. (XTAL2 open, OSCBYP_=GND)
SPLK #00B1h,CKCR1 ; CLKIN(OSC)=10MHz, Mult by 2, Div by 1.
SPLK #0043h,CKCR0 ; CLKMD=PLL disable,SYSCLK=CPUCLK/2,
SPLK #00C3h,CKCR0 ; CLKMD=PLL Enable,SYSCLK=CPUCLK/2,
* Clear reset flag bits in SYSSR (PORRST, PLLRST, ILLRST, SWRST, WDRST)
LACL SYSSR ; ACCL <= SYSSR
AND #00FFh ; Clear upper 8 bits of SYSSR
SACL SYSSR ; Load new value into SYSSR
* Initialize IOPC1/CLKOUT pin for use as DSP clock out
SPLK #40C8h,SYSCR ; No reset, CLKOUT=CPUCLK, VCCA on
* initialize B2 RAM to zero's.
LAR AR1,#B2_SADDR ; AR1 <= B2 start address
MAR *,AR1 ; use B2 start address for next indirect
ZAC ; ACC <= 0
RPT #1fh ; set repeat counter for 1fh+1=20h or 32 loops
SACL *+ ; write zeros to B2 RAM
* initialize DATAOUT with data to be transmitted.
LAR AR1,#DATAOUT ; AR1 <= DATAOUT start address
RPT #06h ; set repeat counter for 6h+1=7h or 7 loops
BLPD #TXDATA,*+ ; loads 60h - 67h with TXDATA
CALL INIT_SPI
* Initialize DSP for interrupts
LAR AR6,#IMR ;
LAR AR7,#IFR ;
MAR *,AR6
LACL #01h ;
SACL *,AR7 ; Enable interrupts 1 only
LACL * ; Clear IFR by reading and
SACL *,AR2 ; writing contents back into itself
CLRC INTM ; Enable DSP interrupts
; Main routine goes here.
MAIN ; Main loop of code begins here ...
; .... ; insert actual code here
NOP
NOP
NOP
; .... ; insert actual code here
B MAIN ; The MAIN program loop has completed one
; pass, branch back to the beginning and
; continue.
*******************************************************************************
* Subroutines *
*******************************************************************************
;===========================================================================
; Routine Name: INIT_SPI Routine Type: SR
;
; Description: This SR initializes the SPI for data stream transfer
; to a master SPI. The '240 SPI is configured for
; 8-bit transfers as a slave.
;
;===========================================================================
INIT_SPI:
* initialize SPI in slave mode
SPLK #0087h,SPICCR ; Reset SPI by writing 1 to SWRST
SPLK #0008h,SPICTL ; Disable ints & TALK, normal clock, slave mode
SPLK #0000h,SPIPRI ; Set SPI interrupt to high priority.
; For emulation purposes, allow the SPI
; to continue after an XDS suspension.
; HAS NO EFFECT ON THE ACTUAL DEVICE.
SPLK #000Eh,SPIBRR ; Set baud rate to 'fastest'
; NOTE: The baud rate should be as fast as possible for communications
; between two or more SPI's. Issues in the baud rate selection to
; remember are the master vs. slave maximum speed differences, and
; to a lessor degree, the clock speed of each device. For DSP
; controllers and PRISM devices this determined by SYSCLK .
;
; A value of '0Eh' in the SPIBRR will insure the fastest available
; baud rate for the master and slave device (assuming two DSP controller
; devices with the same SYSCLK are doing the communication). This is
; case when the master SPI uses a polling routine to determine when
; to transmit the next byte.
SPLK #0000h,SPISTS ; Clear the SPI interrupt status bits
SPLK #0009h,SPICTL ; Disable TALK & RCV int, CLK ph 1, slave mode
SPLK #0022h,SPIPC1 ; Enable the SPISTE and SPICLK pin functions.
; SPISTE will functiion as a transmit enable
; input for the slave SPI module.
SPLK #0022h,SPIPC2 ; Set SIMO & SOMI functions to serial I/O
SPLK #0007h,SPICCR ; Release SWRST, clock polarity 0, 8 bits
* Initialize Auxilliary Registers for SPI receive ISR
LAR AR1,#LENGTH-1 ; load length of data stream into AR1
; and use for transmit/receive loop counter.
LAR AR2,#DATAOUT ; load location of transmit data stream into
; AR2.
LAR AR3,#DATAIN ; load location of receive data stream into
; AR3.
RET ; Return to MAIN routine.
*******************************************************************************
* ISR's *
*******************************************************************************
;==============================================================================
; I S R - INT1 interrupt service routine
;
; Description: This is an implementation of Method 3: ISR for Single Event
; per Interrupt Level (see interrupt section in System Functions
; chapter in Vol 1 of the user's guide).
;
; This ISR performs initial receive of the DECODE byte from the
; master SPI. This byte is checked to determine if the master
; is requesting data from this SPI, and if so, sets the TALK bit
; to enable transmission and writes a byte into SPIDAT
; from DATAOUT. The number of bytes received is controlled
; by the constant LENGTH, which is determined prior to
; assembly.
; The TALK bit is cleared after LENGTH # of bytes have been
; received, and the Auxiliary register pointers are reloaded
; in preparation of the next transfer.
;
;==============================================================================
INT1_ISR ; Interrupt 1 Interrupt Service Routine
MAR *,AR3 ; use location of DATAIN for next indirect
LACL SPIBUF ; ACC <= SPI Buffer Register
SACL *+,AR2 ; store value in B2 @ DATAIN
; use DATAOUT address for next indirect
XOR #DECODE ; compare received byte to determine if slave SPI
; is selected.
BCND SKIP,NEQ
SPLK #000Bh,SPICTL ; Enable TALK & RCV int, CLK ph 1, slave mode
SKIP
LACL *+,AR1 ; ACC <= byte to xmit
; Increment AR2 by one to point to next byte
; in data stream.
; use # bytes left to TX for next indirect address
SACL SPIDAT ; store Xmit byte to SPIDAT and wait for master clock.
BANZ SKIP2,AR2 ; Branch to SKIP2 if AR1 is not zero,
; decrement AR1 by one,
; use DATAOUT address for next address
* Re-Initialize Auxilliary Registers for SPI receive ISR
LAR AR1,#LENGTH-1 ; load length of data stream into AR1
; and use for transmit/receive loop counter.
LAR AR2,#DATAOUT ; load location of transmit data stream into
; AR2.
LAR AR3,#DATAIN ; load location of receive data stream into
; AR3.
* Disable talk after LENGTH # of transfers.
SPLK #0009h,SPICTL ; Disable TALK & RCV int, CLK ph 1, slave mode
SKIP2
CLRC INTM ; Enable DSP interrupts
RET ; Return from interrupt
;==============================================================================
; I S R - PHANTOM
;
; Description: ISR used to trap spurious interrupts.
;
;==============================================================================
PHANTOM
END B END ;
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