📄 div.lst
字号:
0001 * 被除数放到R0中
0002 * 除数防R1中
0003 * OUTPUT: R0/R1 into R0
0004 * REGISTERS USED: R0±R3, IR0, IR1
0005 *
0006 * OPERATION: 1. NORMALIZE DIVISOR WITH DIVIDEND
0007 * 2. REPEAT SUBC
0008 * 3. QUOTIENT IS IN LSBs OF RESULT
0009 *
0010
0011 * PROCESSOR INITIALIZATION FOR THE TMS320C3x
0012
0013 00000002 SIGN .set R2
0014 00000003 TEMPF .set R3
0015 00000011 TEMP .set IR0
0016 00000012 COUNT .set IR1
0017 .global RESET,INIT,BEGIN
0018 .globl DIVI
0019
0020 * REGISTER FROM 808000H (CTRL)
0021 000000 .data
0022 000000 ffffffff MASK .word 0FFFFFFFFH
0023 000001 00809800 BLK0 .word 0809800H ; 片内1K×32bit RAM块0起始地址
0024 000002 00809c00 BLK1 .word 0809C00H ; 片内1K×32bit RAM块1起始地址
0025 000003 00809f00 STCK .word 0809F00H ; 堆栈起始地址
0026 000004 00808000 CTRL .word 0808000H ; Pointer for peripheral±bus me
0027 000005 00000000 DMACTL .word 0000000H ; Init for DMA control (0)
0028 000006 00000000 TIM0CTL .word 0000000H ; Init of timer 0 control (32)
0029 000007 00000000 TIM1CTL .word 0000000H ; Init of timer 1 control (48)
0030 000008 00000000 SERGLOB0 .word 0000000H ; Init of serial 0 glbl control
0031 000009 00000000 SERPRTX0 .word 0000000H ; Init of serial 0 xmt port cont
0032 00000a 00000000 SERPRTR0 .word 0000000H ; Init of serial 0 rcv port cont
0033 00000b 00000000 SERTIM0 .word 0000000H ; Init of serial 0 timer control
0034 00000c 00000000 SERGLOB1 .word 0000000H ; Init of serial 1 glbl control
0035 00000d 00000000 SERPRTX1 .word 0000000H ; Init of serial 1 xmt port cont
0036 00000e 00000000 SERPRTR1 .word 0000000H ; Init of serial 1 rcv port cont
0037 00000f 00000000 SERTIM1 .word 0000000H ; Init of serial 1 timer control
0038 000010 00000000 PARINT .word 0000000H ; Init of parallel interface con
0039 000011 00000000 IOINT .word 0000000H ; Init of I/O interface control
0040 *
0041 000000 .sect "initialize"; Named section
0042 000000 00000000' RESET .word INIT ; RS± load address INIT to PC
0043 000001 00000000 .space 191 ; Reserved space
0044
0045 000000 .text
0046 * THE STATUS REGISTER HAS THE FOLLOWING ARRANGEMENT:
0047 * BITS: 31–14 13 12 11 10 9 8 7 6 5 4 3
0048 * FUNCTION: RESRV GIE CC CE CF RESRV RM OVM LUF LV UF N
0049 *
0050
0051 000000 08700000 INIT: LDP 0,DP ; Point the DP register to page 0
0052 000001 08751800 LDI 1800H,ST ; Clear and enable cache, and disa
0053 000002 08360000+ LDI @MASK,IE ; Unmask all interrupts
0054 000003 08280001+ LDI @BLK0,AR0 ; AR0 points to block 0
0055 000004 08290002+ LDI @BLK1,AR1 ; AR1 points to block 1
0056 000005 07608000 LDF 0.0,R0 ; 0 register R0
0057 000006 13fb03ff RPTS 1023 ; Repeat 1024 times ...
0058 000007 c0002120 STF R0,*AR0++(1) ; Zero out location in RAM blo
0059 || STF R0,*AR1++(1) ; Zero out location in RAM
0060 000008 08280004+ LDI @CTRL,AR0 ; Load in AR0 the pointer to cont
0061 000009 08200005+ LDI @DMACTL,R0
0062 00000a 15400000 STI R0,*+AR0(0) ; Init DMA control
0063 00000b 08200006+ LDI @TIM0CTL,R0
0064 00000c 15400020 STI R0,*+AR0(32) ; Init timer 0 control
0065 00000d 08200007+ LDI @TIM1CTL,R0
0066 00000e 15400030 STI R0,*+AR0(48) ; Init timer 1 control
0067 00000f 08200008+ LDI @SERGLOB0,R0
0068 000010 15400040 STI R0,*+AR0(64) ; Init serial 0 global control
0069 000011 08200009+ LDI @SERPRTX0,R0
0070 000012 15400042 STI R0,*+AR0(66) ; Init serial 0 xmt control
0071 000013 0820000a+ LDI @SERPRTR0,R0
0072 000014 15400043 STI R0,*+AR0(67) ; Init serial 0 rcv control
0073 000015 0820000b+ LDI @SERTIM0,R0
0074 000016 15400044 STI R0,*+AR0(68) ; Init serial 0 timer control
0075 000017 0820000c+ LDI @SERGLOB1,R0
0076 000018 15400050 STI R0,*+AR0(80) ; Init serial 1 global control
0077 000019 0820000d+ LDI @SERPRTX1,R0
0078 00001a 15400052 STI R0,*+AR0(82) ; Init serial 1 xmt control
0079 00001b 0820000e+ LDI @SERPRTR1,R0
0080 00001c 15400053 STI R0,*+AR0(83) ; Init serial 1 rcv control
0081 00001d 0820000f+ LDI @SERTIM1,R0
0082 00001e 15400054 STI R0,*+AR0(84) ; Init serial 1 timer control
0083 00001f 08200010+ LDI @PARINT,R0
0084 000020 15400064 STI R0,*+AR0(100) ; Init parallel interface control (C
0085 000021 08200011+ LDI @IOINT,R0
0086 000022 15400060 STI R0,*+AR0(96) ; Init I/O interface control
0087 000023 08340003+ LDI @STCK,SP ; Init the stack pointer
0088 000024 10752000 OR 2000H,ST ; Global interrupt enable
0089
0090 000025 08600021 DIVI: ldi 33,r0
0091 000026 08610005 ldi 5,r1
0092 000027 28020100 XOR R0,R1,SIGN ; Get the sign
0093 000028 00800000 ABSI R0;被除数取正
0094 000029 00810001 ABSI R1;除数取正
0095 00002a 04810000 CMPI R0,R1 ; Divisor > dividend ?
0096 00002b 6a230012 BHID ZERO ; If so, return 0
0097 00002c 05830000 FLOAT R0,TEMPF ; Normalize dividend
0098 00002d 0fa30000 PUSHF TEMPF ; PUSH as float
0099 00002e 0e320000 POP COUNT ; POP as int
0100 00002f 09f2ffe8 LSH -24,COUNT ; Get dividend exponent
0101 000030 05830001 FLOAT R1,TEMPF ; Normalize divisor
0102 000031 0fa30000 PUSHF TEMPF ; PUSH as float
0103 000032 0e310000 POP TEMP ; POP as int
0104 000033 09f1ffe8 LSH -24,TEMP ; Get divisor exponent
0105 000034 18120011 SUBI TEMP,COUNT ; Get difference in exponents
0106 000035 09810012 LSH COUNT,R1 ; Align divisor with dividend
0107 000036 139b0012 RPTS COUNT
0108 000037 17000001 SUBC R1,R0
0109
0110 * MASK OFF THE LOWER COUNT+1 BITS OF R0.
0111
0112 000038 19f2001f SUBRI 31,COUNT ; Shift count is (32 ± (COUNT+1))
0113 000039 09800012 LSH COUNT,R0 ; Shift left
0114 00003a 0c120012 NEGI COUNT
0115 00003b 09800012 LSH COUNT,R0 ; Shift right to get result
0116 *
0117 * CHECK SIGN AND NEGATE RESULT IF NECESSARY.
0118 *
0119 00003c 0c010000 NEGI R0,R1 ; Negate result
0120 00003d 03e2ffe1 ASH -31,SIGN ; Check sign
0121 00003e 53000001 LDINZ R1,R0 ; If set, use negative result
0122 00003f 04e00000 CMPI 0,R0 ; Set status from result
0123 000040 08600000 ZERO: LDI 0,R0
0124 000041 60000041 BR $
0125 .end
No Errors, No Warnings
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