init_sdr.inc

Redboot, boot-loader of Linux for Freescale ARM family.

clearbreak
bexec 0x00000000
wait = on
reset
pause 2

// ############################################################################
// # i.MX21 EVB v0.0 or v1.0 Initialization (For Tape Out 2 ONLY)
// ############################################################################

// ############################################################################
// # History
// #
// # revision 0.0.1
// # ------------------------------------------------------
// # 1. Update CS1 Setting
// # 2. Update PTF_GIUSE and PTF_GPR setting for PF18 as CS1
// # 3. Disable LCDC
// # 4. Add Master Priority Register for Slave Port 3
// #
// # revision 0.0.2
// # ------------------------------------------------------
// # 1. Add LCD Init for Sharp LCD (Part#: LQ035Q2DD54)
// # 2. Change HCLK to 88MHz
// # 3. Change CS3 Setting for SRAM on Base Board
// #
// # revision 0.0.3
// # ------------------------------------------------------
// # 1. Clear HCLK_LCDC_EN and LCDC_PIXCLK_EN for disable LCD before memory init.
// # 2. Change the HM and TM for LCDC DMA
// # 3. Change the CrossBar Setting.
// # 4. Add 1 to EDC bits of CS0 and CS3 register setting
// # 5. Change the wait state of CS0 and CS3 to 0xE
// # 
// # revision 0.0.4 (For Tape OUT 2 only)
// # ------------------------------------------------------
// # 1. Add Setting for MPCTL0 register.
// # 2. Change value in CSCR register for Tape Out 2.
// # 3. Change the address of PCCR0 Register for Tape Out 2.
// # 4. Add PCDR1 register setting to enable LCDC for Tape Out 2.
// # 
// # revision 0.0.5 (For Tape OUT 2 only)
// # ------------------------------------------------------
// # 1. Remove the PLL setting. The MPLL_RESTART bit will hold up the JTAG. 
// #    The communication between AXD and JTAG will be broken. The PLL is needed
// #    to be programmed inside user program.
// #
// # revision 0.0.6 (For Tape OUT 2 only)
// # ------------------------------------------------------
// # 1. Turn on the back light.
// #
// # revision 0.0.7 (For Tape OUT 2 only)
// # ------------------------------------------------------
// # 1. Change the driving of LCD signals to solve the LCD display problem.
// #    Because the default driving is too high, LCD display problem exists.
// ############################################################################

// ############################################################################
// ###
// ### AHB-Lite IP Interface
// ###
// ############################################################################
setmem /32 0x10000000= 0x00040304
setmem /32 0x10020000= 0x00000000
setmem /32 0x10000004= 0xFFFBFCFB
setmem /32 0x10020004= 0xFFFFFFFF

// ### PCCR0 (Disable LCDC by clear PERCLK3_EN bit)
setmem /32 0x10027020= 0x31084003



// ############################################################################
// ###
// ### EIM
// ###
// ############################################################################

// # CS0 Initialization (Async Mode)     
// # 32-bit, ?? wait states              
setmem /32 0xDF001000= 0x00000E01
setmem /32 0xDF001004= 0x00000E01

// # Setting for Memory Map IO Port
// # CS1 Initialization (Async Mode)
// # 16-bit, D0..15, ?? wait states
setmem /32 0xDF001008= 0x00002000
setmem /32 0xDF00100C= 0x11118501

// # Config MUX for pin PF18->CS1
// # Clear PTF_GIUSE 
setmem /32 0x10015520= 0x00000000
// # Clear PTF_GPR
setmem /32 0x10015538= 0x00000000

// # CS3 Initialization (Async Mode) SRAM on EVB Base Board
// # 32-bit, ?? wait states
setmem /32 0xDF001018= 0x00000A00
setmem /32 0xDF00101C= 0x11110601

// # FMCR Register
// # Select CS3/CSD0 Pin as CS3 only.
setmem /32 0x10027814= 0xFFFFFFC9

// ############################################################################
// ###
// ### SDRAMC
// ###
// ############################################################################

// ########################################################
// # CSD0 Initialization (SDRAM)   
// # 16Mx16x2 IAM=0 CSD0 CL3 
// ########################################################

// *** Set Precharge Command
setmem /32 0xDF000000= 0x92120300

// *** Issue Precharge all Command
dump /32 0xC0200000..+4          

// *** Set AutoRefresh Command
setmem /32 0xDF000000= 0xA2120300

// *** Issue AutoRefresh Command
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4
dump /32 0xC0000000..+4

// *** Set Mode Register
setmem /32 0xDF000000= 0xB2120300

// *** Issue Mode Register Command
// Burst Length = 8
dump /32 0xC0119800..+4

// *** Set to Normal Mode
// # From the spec of the SDRAM K4S56163LC-RG75000, 
// # 1. tRCD = 19ns minimum  -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b 
// # 2. tRP  = 19ns minimum  -> RP  = 3 clk (SDCLK=133MHz) -> SRP  = 0b 
// # 3. tRC  = 65ns minimum  -> RC  = 9 clk (SDCLK=133MHz) -> SRC  = 1001b 
// # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
setmem /32 0xDF000000= 0x8212F339

// ### End of Memory Configuration ##########################################

// ############################################################################
// ###
// ### CrossBar (MAX)
// ###
// ############################################################################
// ### Master Priority Register for Slave Port 3 (EMI)
// ### LCD - highest priority
// ### ARM - Lowest prority
setmem /32 0x1003F300= 0x00123056

// ############################################################################
// ###
// ### LCD
// ###
// ############################################################################

// ###################
// # Driving
// ###################
// # DSCR1: Driving Strength Control Register
setmem /32 0x10027820= 0x00000000

// ##########################################################################
// # Sharp LCD (Part#: LQ035Q7DB02) Initialization for i.MX21EVB v0.0 Rev 1
// ##########################################################################

// ### PCDR1 Peripheral Clock Divider Register - Set PERDIV3
setmem /32 0x1002701C= 0x03070F0F
//                ^
//                |
//                +- PERDIV3

// ###########################################
//   LCD OFF by bit 9 Memory Map IO Register
// ###########################################
setmem /16 0xCC800000= 0x0000

// ### PCCR0 (Set HCLK_LCDC_EN)
setmem /32 0x10027020= 0x35084003

// ###########################################
// ## Init LCDC 
// ###########################################

// ###############
// ## IO Port
// ###############

// ## Clear Port A for LCD signals
// Port A PTA_GIUS
setmem /32 0x10015020= 0x00000000
// Port A PTA_GPR
setmem /32 0x10015038= 0x00000000

// #######################
// ## LCDC Configuartion
// #######################

// ### Screen Starting Address Register
// # Point to SDRAM
setmem /32 0x10021000= 0xC2000000

// ### Size Register
setmem /32 0x10021004= 0x00F00140

// ### Virtual Page Width
setmem /32 0x10021008= 0x00000078

// ### Cursor
setmem /32 0x1002100C= 0x40010001
setmem /32 0x10021010= 0x1F1F0000
setmem /32 0x10021014= 0x0000F800

// ### Cursor OFF
// ### setmem 0x1002100C 0x00000000 32

// ### Panel Configuration Register

// ## 18-bpp
// setmem 0x10021018 0xFD148BC7 32
// ## 16-bpp
setmem /32 0x10021018= 0xFB148BC7

// ### Sharp Configuration Register
setmem /32 0x10021028= 0x00120300

// hsyn width = 12  hsyn_wait 1 = 15 hsyn_wait2 = 15
setmem /32 0x1002101C= 0x04000F06

// vsyn width = 1  vsyn_wait 1 = 0 vsyn_wait2 = 4
setmem /32 0x10021020= 0x04000907

// LPCCR Register (Set CLS_HI_WIDTH) without backlight
// setmem 0x1002102C 0x00A90200, 32
// LPCCR Register (Set CLS_HI_WIDTH) with backlight
setmem /32 0x1002102C= 0x00A903FF

// Refresh Mode Control Register
setmem /32 0x10021034= 0x00000000

// ### LDCR Register (LCDC DMA)
setmem /32 0x10021030= 0x00020008

// ### Enable LCDC
// ### HCLK_LCDC_EN = 1 and LCDC_PIXCLK_EN = 1
// ### PCCR0
setmem /32 0x10027020= 0x350C4003

// ###########################################
// # LCD ON by bit 9 Memory Map IO Register
// ###########################################
setmem /16 0xCC800000= 0x200

// ############################################################################
// ###
// ### PLL and Clock Setting
// ###
// ############################################################################

// #####################################
// # CLKO Select
// #####################################
// ## CCSR (Set CLKO_SEL = CLK32)
setmem /32 0x10027028= 0x00000300
// ## CCSR (Set CLKO_SEL = FCLK)
// setmem 0x10027028 0x00000307 32
// ## CCSR (Set CLKO_SEL = HCLK)
setmem /32 0x10027028= 0x00000308

// ###### MPCTL0: (For 32.768KHz Input Frequency)
// #      MPLL = 266MHz
// setmem 0x10027004 0x007B1C73 32

// #### Select the Frequency
// ### CSCR: FCLK=MPLL/1; HCLK=FCLK/2; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=133MHz)
// ### setmem 0x10027000 0x17000607 32
// ### CSCR: FCLK=MPLL/1; HCLK=FCLK/3; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=88MHz)
// ##  setmem 0x10027000 0x17000A07 32
// ### CSCR: FCLK=MPLL/1; HCLK=FCLK/4; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=66MHz)
setmem /32 0x10027000= 0x17000E07
// ### CSCR: FCLK=MPLL/1; HCLK=FCLK/8; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=33MHz)
// ##  setmem 0x10027000 0x17001E07 32

// maximize drive strength of address, data, and control signals
// setmem 0x10027824 0x7FFF7FFF 32
// setmem 0x10027828 0x7FFF7FFF 32
// setmem 0x1002782C 0x7FFF7FFF 32
// setmem 0x10027830 0x7FFF7FFF 32
// setmem 0x10027834 0x7FFF7FFF 32
// setmem 0x10027838 0x7FFF7FFF 32
// setmem 0x1002783C 0x7FFF7FFF 32
// setmem 0x10027840 0x7FC07FF8 32
// setmem 0x10027844 0x7FFF7FFF 32
// setmem 0x10027848 0x7FFF7FFF 32
// lb "D:\cygwin\src\ecos\install\bin\redboot.bin", 0xC2000000

readfile,raw,gui "r:\tftp\mx21ads_redboot.bin"=0xC3F00000
setreg @R15=0xC3F00000