chandle.c

Redboot, boot-loader of Linux for Freescale ARM family.

	if(((AITC_NIPRIORITY3>>16)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x10000000;		// clear the bit in the force reg.
}

void   norm_scr27_isr(void)	// norm_scr27_isr (27)
{
    if((AITC_NIPNDL & 0x08000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY3>>12)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x08000000;		// clear the bit in the force reg.

}

void   norm_scr26_isr(void)	// norm_scr26_isr (26)
{
    if((AITC_NIPNDL & 0x04000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY3>>8)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x04000000;		// clear the bit in the force reg.

}

void   norm_scr25_isr(void)	// norm_scr25_isr (25)
{
    if((AITC_NIPNDL & 0x02000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY3>>4)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x02000000;		// clear the bit in the force reg.
}

void   norm_scr24_isr(void)	// norm_scr24_isr (24)
{
    if((AITC_NIPNDL & 0x01000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY3)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x01000000;		// clear the bit in the force reg.
}

void   norm_scr23_isr(void)	// norm_scr23_isr (23)
{
    if((AITC_NIPNDL & 0x00800000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>28)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00800000;		// clear the bit in the force reg.
}

void   norm_scr22_isr(void)	// norm_scr22_isr (22)
{
    if((AITC_NIPNDL & 0x00400000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>24)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00400000;		// clear the bit in the force reg.
}

void   norm_scr21_isr(void)	// norm_scr21_isr (21)
{
    if((AITC_NIPNDL & 0x00200000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>20)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00200000;		// clear the bit in the force reg.
}

void   norm_scr20_isr(void)	// norm_scr20_isr (20)
{
    if((AITC_NIPNDL & 0x00100000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>16)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00100000;		// clear the bit in the force reg.
}

void   norm_scr19_isr(void)	// norm_scr19_isr (19)
{
    if((AITC_NIPNDL & 0x00080000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>12)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00080000;		// clear the bit in the force reg.
}

void   norm_scr18_isr(void)	// norm_scr18_isr (18)
{
    if((AITC_NIPNDL & 0x00040000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>8)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}


    *(p_uint32_t) AITC_INTFRCL &= ~0x00040000;		// clear the bit in the force reg.
}

void   norm_scr17_isr(void)	// norm_scr17_isr (17)
{
    if((AITC_NIPNDL & 0x00020000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2>>4)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00020000;			// clear the bit in the force reg.
    //gNormInt17flag = 1;				// set flag
	printf("IRQ source 17 is success\n");
}

void   norm_scr16_isr(void)	// norm_scr16_isr (16)
{
    if((AITC_NIPNDL & 0x00010000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY2)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00010000;			// clear the bit in the force reg.
    gNormInt16flag = 1;				// set flag
	printf("IRQ source 16 is success\n");	
}

void   norm_scr15_isr(void)	// norm_scr15_isr (15)
{
    if((AITC_NIPNDL & 0x00008000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>28)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00008000;			// clear the bit in the force reg.
    gNormInt15flag = 1;				// set flag
	printf("IRQ source 15 is success\n");	
}

void   norm_scr14_isr(void)	// norm_scr14_isr (14)
{
    if((AITC_NIPNDL & 0x00004000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>24)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}
    *(p_uint32_t) AITC_INTFRCL &= ~0x00004000;			// clear the bit in the force reg.
    gNormInt14flag = 1;				// set flag
	printf("IRQ source 14 is success\n");
}

void   norm_scr13_isr(void)	// norm_scr13_isr (13)
{
    if((AITC_NIPNDL & 0x00002000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>20)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00002000;			// clear the bit in the force reg.
    gNormInt13flag = 1;				// set flag
	printf("IRQ source 13 is success\n");
}

void   norm_scr12_isr(void)	// norm_scr12_isr (12)
{
    if((AITC_NIPNDL & 0x00001000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>16)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00001000;			// clear the bit in the force reg.
    gNormInt12flag = 1;				// set flag
	printf("IRQ source 12 is success\n");
}

void   norm_scr11_isr(void)	// norm_scr11_isr (11)
{
    if((AITC_NIPNDL & 0x00000800) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>12)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000800;			// clear the bit in the force reg.
    gNormInt11flag = 1;				// set flag
	printf("IRQ source 11 is success\n");

}

void   norm_scr10_isr(void)	// norm_scr10_isr (10)
{
    if((AITC_NIPNDL & 0x00000400) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>8)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000400;		// clear the bit in the force reg.
    gNormInt10flag = 1;			// set flag
	printf("IRQ source 10 is success\n");	
}

void   norm_scr09_isr(void)	// norm_scr09_isr  (9)
{
    if((AITC_NIPNDL & 0x00000200) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1>>4)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000200;		// clear the bit in the force reg.
    gNormInt9flag = 1;			// set flag
	printf("IRQ source 9 is success\n");
}

void   norm_scr08_isr(void)	// norm_scr08_isr  (8)
{
    if((AITC_NIPNDL & 0x00000100) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY1)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000100;		// clear the bit in the force reg.
    gNormInt8flag = 1;			// set flag
	printf("IRQ source 8 is success\n");
}

void   norm_scr07_isr(void)	// norm_scr07_isr  (7)
{
    if((AITC_NIPNDL & 0x00000080) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>28)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000080;		// clear the bit in the force reg.
    gNormInt7flag = 1;			// set flag
	printf("IRQ source 7 is success\n");
}

void   norm_scr06_isr(void)	// norm_scr06_isr  (6)
{
    if((AITC_NIPNDL & 0x00000040) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>24)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000040;		// clear the bit in the force reg.
    gNormInt6flag = 1;				// set flag
	printf("IRQ source 6 is success\n");
}

void   norm_scr05_isr(void)	// norm_scr05_isr  (5)
{
    if((AITC_NIPNDL & 0x00000020) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>20)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000020;		// clear the bit in the force reg.
    gNormInt5flag = 1;				// set flag
	printf("IRQ source 5 is success\n");
}

void   norm_scr04_isr(void)	// norm_scr04_isr  (4)
{
    if((AITC_NIPNDL & 0x00000010) == 0)	// verify the pending bit is set
    {
        	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>16)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000010;	// clear the bit in the force reg.
    gNormInt4flag = 1;				// set flag
	printf("IRQ source 4 is success\n");
}

void   norm_scr03_isr(void)	// norm_scr03_isr  (3)
{
    if((AITC_NIPNDL & 0x00000008) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>12)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000008;		// clear the bit in the force reg.
    gNormInt3flag = 1;				// set flag
	printf("IRQ source 3 is success\n");
}

void   norm_scr02_isr(void)	// norm_scr02_isr  (2)
{
    if((AITC_NIPNDL & 0x00000004) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>8)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000004;		// clear the bit in the force reg.
    gNormInt2flag = 1;				// set flag
    printf("IRQ source 2 is success\n");
}

void   norm_scr01_isr(void)	// norm_scr01_isr  (1)
{
    if((AITC_NIPNDL & 0x00000002) == 0)
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0>>4)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000002;		// clear the bit in the force reg.
    gNormInt1flag = 1;				// set flag
	printf("IRQ source 1 is success\n");		
}

void   norm_scr00_isr(void)	// norm_scr00_isr  (0)
{
    if((AITC_NIPNDL & 0x00000001) == 0)
    {
    	gFailPendingCount++;
    }	

	if(((AITC_NIPRIORITY0)&0xF)!=(AITC_NIVECSR&0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t) AITC_INTFRCL &= ~0x00000001;		// clear the bit in the force reg.
    gNormInt0flag = 1;			// set flag
    printf("IRQ source 0 is success\n");
}