init_sdram_investigation.s

Redboot, boot-loader of Linux for Freescale ARM family.

        AREA    Init, CODE, READONLY

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled

; --- Amount of memory (in bytes) allocated for stacks

Len_FIQ_Stack    EQU     1024
Len_IRQ_Stack    EQU     1024
Len_ABT_Stack    EQU     1024
Len_UND_Stack    EQU     1024
Len_SVC_Stack    EQU     1024
Len_USR_Stack    EQU     1024


; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.

Offset_FIQ_Stack         EQU     0
Offset_IRQ_Stack         EQU     Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack         EQU     Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack         EQU     Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack         EQU     Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack         EQU     Offset_SVC_Stack + Len_SVC_Stack

        ENTRY

        EXPORT  Reset_Handler

Reset_Handler

	bl MMU_Setup
	bl PrvFlushCacheAndTLB_AND_DisableCaches
	
			
	;; enable I/D caches and MMU
    MRC p15,0,r1,c1,c0,0
    LDR r2, =(0x00001005)
    
    
    orr r1,r2,r1
    MCR p15,0,r1,c1,c0,0	

; --- Initialize stack pointer registers

; Enter each mode in turn and set up the stack pointer

       IMPORT  top_of_stacks       ; defined in stack.s and located by scatter file
;       LDR     r0, =top_of_stacks
       LDR     r0, =(0xC2000000)	; define stack to be in SDRAM
;       LDR     r0, =(0xD1010000)	; define stack to be in SRAM

       MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
       SUB     sp, r0, #Offset_FIQ_Stack

       MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
       SUB     sp, r0, #Offset_IRQ_Stack

       MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
       SUB     sp, r0, #Offset_ABT_Stack

;       MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
;       SUB     sp, r0, #Offset_UND_Stack

       MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
       SUB     sp, r0, #Offset_SVC_Stack

; --- Initialize memory system

; --- Potential SDRAM issue

	mov r0,#1
  	mov r1,#2
  	mov r2,#3
  	mov r3,#4
  	mov r4,#5
  	mov r5,#6
  	mov r6,#7
  	mov r7,#8
  	mov r8,#9
  	mov r9,#10
  	mov r10,#11
 	mov r11,#12
  	mov r12,#13
  
 
  	stmdb sp!,{r0-r11}
  	ldmia sp!,{r0-r11}


; --- Initialize critical IO devices

; --- Now change to User mode and set up User mode stack, if needed
;        MSR     CPSR_c, #Mode_USR:OR:I_Bit:OR:F_Bit ; No interrupts
;        SUB     sp, r0, #Offset_USR_Stack
                
        IMPORT  __main

; --- Now enter the C code
        B       __main   ; note use B not BL, because an application will never return this way

	LTORG		;// place LTORG here, before the MMU translation table, but after all other LDR commands
	        
    GBLA	XCount
       
MMUTranslationTable


	IF :DEF: MX1
;// DBMX1 translation table
XCount	SETA	(0x0000007E) 
		DCD	XCount
XCount	SETA	(0x0010007E) 
		DCD	XCount
XCount	SETA	(0x00200072) 
		DCD	XCount		
;XCount	SETA	(0x00300072) ; Use 0x72 for non-cacheable, non-bufferable
XCount	SETA	(0x0030007A) ; Use 0x7A for cacheable only
;XCount	SETA	(0x0030007E) ; Use 0x7E for both cacheable and bufferable. 
	WHILE XCount < (0x10000000)
		DCD	XCount
XCount	SETA	(XCount + 0x00100000)
	WEND

XCount	SETA	(0x1000007A) ; Use 0x7A for cacheable only
	WHILE XCount < (0xFFF00000)		
		DCD	XCount
XCount	SETA	(XCount + 0x00100000)
	WEND

;// 0xFFF00000 to end of memory map
XCount	SETA	(0xFFF0007E)	; Use 0x7E for both cacheable and bufferable.  	
		DCD	XCount
		
	ELSE
;// DBMX21 translation table	

;// 0x0 to 0x0FFFFFFF	
XCount	SETA	(0x0000007E)	; Use 0x7E for both cacheable and bufferable.  	
	WHILE XCount < (0x10000000)		
		DCD	XCount
XCount	SETA	(XCount + 0x00100000)
	WEND	

;// 0x10000000 to 0xBFFFFFFF
XCount	SETA	(0x10000072)	; Use 0x72 for non-cacheable, non-bufferable
	WHILE XCount < (0xC0000000)		
		DCD	XCount
XCount	SETA	(XCount + 0x00100000)
	WEND	

;// 0xC0000000 to 0xDFFFFFFF
XCount	SETA	(0xC000007E)	; Use 0x7E for both cacheable and bufferable.  	
	WHILE XCount < (0xE0000000)		
		DCD	XCount
XCount	SETA	(XCount + 0x00100000)
	WEND

;// 0xE0000000 to 0xFFEFFFFF
XCount	SETA	(0xE000007E)	; Use 0x7E for both cacheable and bufferable.  	
	WHILE XCount < (0xFFF00000)		
		DCD	XCount
XCount	SETA	(XCount + 0x00100000)
	WEND

;// 0xFFF00000 to end of memory map
XCount	SETA	(0xFFF0007E)	; Use 0x7E for both cacheable and bufferable.  	
		DCD	XCount

	ENDIF
	
EndOfTables

	

MMU_Setup
	LDR	r0, =0x4000	; target address = 0x4000
	
	IF :DEF: MX1
	;// i.MX1 SDRAM location
	add	r0, r0, #0x0B000000;  Physical target address, fourth bank of SDRAM
	ELSE
	;// i.MX21 SDRAM location
	add	r0, r0, #0xC3000000;  Physical target address, fourth bank of SDRAM
	ENDIF
	
	
	ADRL	r1, MMUTranslationTable			; source address
	ADR	r2, EndOfTables					; limit of source

copyloop1
		ldmia	r1!, {r3-r7}
		stmia	r0!, {r3-r7}
		subs	r3, r1, r2
		blt		copyloop1


	LDR	r0, =0x555555f1
	MCR	p15, 0, r0, c3, c0, 0

	;; make the translation table base ptr point to our table
	IF :DEF: MX1
	;// i.MX1 SDRAM location
	LDR	r0, =0x0B004000		;MMUTranslationTableAddr
	ELSE
	;// i.MX21 SDRAM location	
	LDR	r0, =0xC3004000		;MMUTranslationTableAddr
	ENDIF
	
	MCR	p15, 0, r0, c2, c0, 0

	bx	lr  





PrvFlushCacheAndTLB_AND_DisableCaches

	ldr	r1, =0x00000000

	;; Drain the write buffer
	mcr	p15, 0, r1, c7, c10, 4

	;; Clean and Flush the Cache
	mcr	p15, 0, r1, c7, c7, 0

	;; Flush the TLB
	mcr	p15, 0, r1, c8, c7, 0

	;; Read the coprocessor control register
	mrc	p15, 0, r1, c1, c0, 0
	mov	r2, #0x00001000
	add	r2, r2, #0x4
	bic r1, r1, r2
	
	;write to control register
	mcr p15, 0, r1, c1, c0, 0

	BX	lr


        END