initredboot.txt

Redboot, boot-loader of Linux for Freescale ARM family.

comment ########################################################
comment # i.MX21 EVB v0.0 Initialization
comment ########################################################

comment ########################################################
comment # History
comment #
comment # revision 0.0.1
comment # ------------------------------------------------------
comment # 1. Update CS1 Setting
comment # 2. Update PTF_GIUSE and PTF_GPR setting for PF18 as CS1
comment # 3. Disable LCDC
comment # 4. Add Master Priority Register for Slave Port 3
comment #
comment # revision 0.0.2
comment # ------------------------------------------------------
comment # 1. Add LCD Init for Sharp LCD (Part#: LQ035Q2DD54)
comment # 2. Change HCLK to 88MHz
comment # 3. Change CS3 Setting for SRAM on Base Board
comment #
comment ########################################################

comment #################
comment # AHB-Lite IP Interface
setmem 0x10000000 0x00040304 32
setmem 0x10020000 0x00000000 32
setmem 0x10000004 0xFFFBFCFB 32
setmem 0x10020004 0xFFFFFFFF 32

comment ##############################
comment ## PLL
comment ## HCLK 33MHz
comment setmem 0x10027000 0x1700c607 32
comment ## HCLK 66MHz
setmem 0x10027000 0x1700c207 32
comment ## HCLK 88MHz
comment setmem 0x10027000 0x17000a07 32
comment ## HCLK 133MHz
comment setmem 0x10027000 0x17000607 32

comment # CS0 Initialization (Async Mode)     
comment # 32-bit, ?? wait states              
setmem 0xDF001000 0x00003E00 32
setmem 0xDF001004 0x00000E01 32

comment # Setting for Memory Map IO Port
comment # CS1 Initialization (Async Mode)
comment # 16-bit, D0..15, ?? wait states
setmem 0xDF001008 0x00002000 32
setmem 0xDF00100C 0x11118501 32

comment # CS3 Initialization (Async Mode)
comment # 32-bit, ?? wait states
setmem 0xDF001018 0x00003E00 32
setmem 0xDF00101C 0x11110601 32

comment # Config MUX for pin PF18->CS1
comment # Clear PTF_GIUSE 
setmem 0x10015520 0x00000000 32
comment # Clear PTF_GPR
setmem 0x10015538 0x00000000 32

comment # FMCR Register
comment # Select CS3/CSD0 Pin as CS3 only.
setmem 0x10027814 0xFFFFFFC9 32

comment ### PCCR0 (Disable LCDC)
setmem 0x1002701C 0x35084003 32

comment ### Master Priority Register for Slave Port 3
setmem 0x1003F300 0x00123456 32

comment ########################################################
comment # CSD0 Initialization    
comment # 16Mx16x2 IAM=0 CSD0 CL3 
comment ########################################################

comment *** Set Precharge Command
setmem 0xDF000000 0x92120300 32

comment *** Issue Precharge all Command
memory 0xC0200000 +1 32          

comment *** Set AutoRefresh Command
setmem 0xDF000000 0xA2120300 32 

comment *** Issue AutoRefresh Command
memory 0xC0000000 +1 32         
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32         
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32

comment *** Set Mode Register
setmem 0xDF000000 0xB2120300 32

comment *** Issue Mode Register Command
comment Burst Length = 8
memory 0xC0119800 +1 32           

comment *** Set to Normal Mode
comment # From the spec of the SDRAM K4S56163LC-RG75000, 
comment # 1. tRCD = 19ns minimum  -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b 
comment # 2. tRP  = 19ns minimum  -> RP  = 3 clk (SDCLK=133MHz) -> SRP  = 0b 
comment # 3. tRC  = 65ns minimum  -> RC  = 9 clk (SDCLK=133MHz) -> SRC  = 1001b 
comment # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
setmem 0xDF000000 0x8212F339 32 

comment ### End of Memory Configuration ##########################################

comment ##########################################################################
comment # Sharp LCD (Part#: LQ035Q2DD54) Initialization for i.MX21EVB v0.0 Rev 1
comment ##########################################################################

comment ### Peripheral Clock Divider Register
setmem 0x10027018 0x65593307 32 

comment ############
comment   LCD OFF by bit 9 Memory Map IO Register
comment ############
setmem 0xCC800000 0x0000 16

comment ### PCCR0 (Disable LCDC)
setmem 0x1002701C 0x35084003 32

comment ###########################################
comment ## Init LCDC 
comment ###########################################

comment ###############
comment ## IO Port
comment ###############

comment ## Clear Port A for LCD signals
comment Port A PTA_GIUS
setmem 0x10015020 0x00000000 32
comment Port A PTA_GPR
setmem 0x10015038 0x00000000 32

comment #######################
comment ## LCDC Configuartion
comment #######################

comment ### Screen Starting Address Register
comment # Point to SDRAM
setmem 0x10021000 0xC2000000 32

comment ### Size Register
setmem 0x10021004 0x00F00140 32

comment ### Virtual Page Width
setmem 0x10021008 0x00000078 32

comment ### Cursor
setmem 0x1002100C 0x40010001 32
setmem 0x10021010 0x1F1F0000 32
setmem 0x10021014 0x0000F800 32

comment ### Cursor OFF
comment ### setmem 0x1002100C 0x00000000 32

comment ### Panel Configuration Register

comment ## 18-bpp
comment setmem 0x10021018 0xFC148BC7 32
comment ## 16-bpp
setmem 0x10021018 0xFA148BC7 32

comment ### Sharp Configuration Register
setmem 0x10021028 0x00120300 32

comment hsyn width = 12  hsyn_wait 1 = 15 hsyn_wait2 = 15
setmem 0x1002101C 0x04000F06, 32

comment vsyn width = 1  vsyn_wait 1 = 0 vsyn_wait2 = 4
setmem 0x10021020 0x04000907, 32

comment LPCCR Register (Set CLS_HI_WIDTH)
setmem 0x1002102C 0x00A90200, 32

comment Refresh Mode Control Register
setmem 0x10021034 0x00000000, 32

comment ### LDCR Register (LCDC DMA)
setmem 0x10021030 0x800D0002, 32

comment ### Enable LCDC

comment ### PCCR0
setmem 0x1002701C 0x350C4003 32

comment ###########################################
comment # LCD ON by bit 9 Memory Map IO Register
comment ###########################################
setmem 0xCC800000 0x200 16



comment lb "D:\cygwin\src\ecos\install\bin\redboot.bin", 0xC2000000
comment lb "D:\cygwin\src\ecos\install\bin\redboot.bin", 0xC2000000
comment setpc 0xc2000000
comment setpc 0xC0800000


comment ld "d:\Symbian\OS7s_03073a_beech\axd\MX2\SyncFlashProg\EIM_AMD_FLASH_Programming\Project\EIM_AMD_flash_programming_Data\Debug\EIM_AMD_flash_programming.axf"