initredboot.txt

Redboot, boot-loader of Linux for Freescale ARM family.

comment ############################################################################
comment # i.MX21 EVB v0.0 or v1.0 Initialization (For Tape Out 2 ONLY)
comment ############################################################################

comment ############################################################################
comment # History
comment #
comment # revision 0.0.1
comment # ------------------------------------------------------
comment # 1. Update CS1 Setting
comment # 2. Update PTF_GIUSE and PTF_GPR setting for PF18 as CS1
comment # 3. Disable LCDC
comment # 4. Add Master Priority Register for Slave Port 3
comment #
comment # revision 0.0.2
comment # ------------------------------------------------------
comment # 1. Add LCD Init for Sharp LCD (Part#: LQ035Q2DD54)
comment # 2. Change HCLK to 88MHz
comment # 3. Change CS3 Setting for SRAM on Base Board
comment #
comment # revision 0.0.3
comment # ------------------------------------------------------
comment # 1. Clear HCLK_LCDC_EN and LCDC_PIXCLK_EN for disable LCD before memory init.
comment # 2. Change the HM and TM for LCDC DMA
comment # 3. Change the CrossBar Setting.
comment # 4. Add 1 to EDC bits of CS0 and CS3 register setting
comment # 5. Change the wait state of CS0 and CS3 to 0xE
comment # 
comment # revision 0.0.4 (For Tape OUT 2 only)
comment # ------------------------------------------------------
comment # 1. Add Setting for MPCTL0 register.
comment # 2. Change value in CSCR register for Tape Out 2.
comment # 3. Change the address of PCCR0 Register for Tape Out 2.
comment # 4. Add PCDR1 register setting to enable LCDC for Tape Out 2.
comment # 
comment # revision 0.0.5 (For Tape OUT 2 only)
comment # ------------------------------------------------------
comment # 1. Remove the PLL setting. The MPLL_RESTART bit will hold up the JTAG. 
comment #    The communication between AXD and JTAG will be broken. The PLL is needed
comment #    to be programmed inside user program.
comment #
comment # revision 0.0.6 (For Tape OUT 2 only)
comment # ------------------------------------------------------
comment # 1. Turn on the back light.
comment #
comment # revision 0.0.7 (For Tape OUT 2 only)
comment # ------------------------------------------------------
comment # 1. Change the driving of LCD signals to solve the LCD display problem.
comment #    Because the default driving is too high, LCD display problem exists.
comment ############################################################################

comment ############################################################################
comment ###
comment ### AHB-Lite IP Interface
comment ###
comment ############################################################################
setmem 0x10000000 0x00040304 32
setmem 0x10020000 0x00000000 32
setmem 0x10000004 0xFFFBFCFB 32
setmem 0x10020004 0xFFFFFFFF 32

comment ### PCCR0 (Disable LCDC by clear PERCLK3_EN bit)
setmem 0x10027020 0x31084003 32



comment ############################################################################
comment ###
comment ### EIM
comment ###
comment ############################################################################

comment # CS0 Initialization (Async Mode)     
comment # 32-bit, ?? wait states              
setmem 0xDF001000 0x00000E01 32
setmem 0xDF001004 0x00000E01 32

comment # Setting for Memory Map IO Port
comment # CS1 Initialization (Async Mode)
comment # 16-bit, D0..15, ?? wait states
setmem 0xDF001008 0x00002000 32
setmem 0xDF00100C 0x11118501 32

comment # Config MUX for pin PF18->CS1
comment # Clear PTF_GIUSE 
setmem 0x10015520 0x00000000 32
comment # Clear PTF_GPR
setmem 0x10015538 0x00000000 32

comment # CS3 Initialization (Async Mode) SRAM on EVB Base Board
comment # 32-bit, ?? wait states
setmem 0xDF001018 0x00000A00 32
setmem 0xDF00101C 0x11110601 32

comment # FMCR Register
comment # Select CS3/CSD0 Pin as CS3 only.
setmem 0x10027814 0xFFFFFFC9 32

comment ############################################################################
comment ###
comment ### SDRAMC
comment ###
comment ############################################################################

comment ########################################################
comment # CSD0 Initialization (SDRAM)   
comment # 16Mx16x2 IAM=0 CSD0 CL3 
comment ########################################################

comment *** Set Precharge Command
setmem 0xDF000000 0x92120300 32

comment *** Issue Precharge all Command
memory 0xC0200000 +1 32          

comment *** Set AutoRefresh Command
setmem 0xDF000000 0xA2120300 32 

comment *** Issue AutoRefresh Command
memory 0xC0000000 +1 32         
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32         
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32
memory 0xC0000000 +1 32

comment *** Set Mode Register
setmem 0xDF000000 0xB2120300 32

comment *** Issue Mode Register Command
comment Burst Length = 8
memory 0xC0119800 +1 32           

comment *** Set to Normal Mode
comment # From the spec of the SDRAM K4S56163LC-RG75000, 
comment # 1. tRCD = 19ns minimum  -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b 
comment # 2. tRP  = 19ns minimum  -> RP  = 3 clk (SDCLK=133MHz) -> SRP  = 0b 
comment # 3. tRC  = 65ns minimum  -> RC  = 9 clk (SDCLK=133MHz) -> SRC  = 1001b 
comment # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
setmem 0xDF000000 0x8212F339 32 

comment ### End of Memory Configuration ##########################################

comment ############################################################################
comment ###
comment ### CrossBar (MAX)
comment ###
comment ############################################################################
comment ### Master Priority Register for Slave Port 3 (EMI)
comment ### LCD - highest priority
comment ### ARM - Lowest prority
setmem 0x1003F300 0x00123056 32

comment ############################################################################
comment ###
comment ### LCD
comment ###
comment ############################################################################

comment ###################
comment # Driving
comment ###################
comment # DSCR1: Driving Strength Control Register
setmem 0x10027820 0x00000000 32

comment ##########################################################################
comment # Sharp LCD (Part#: LQ035Q7DB02) Initialization for i.MX21EVB v0.0 Rev 1
comment ##########################################################################

comment ### PCDR1 Peripheral Clock Divider Register - Set PERDIV3
setmem 0x1002701C 0x03070F0F 32 
comment                ^
comment                |
comment                +- PERDIV3

comment ###########################################
comment   LCD OFF by bit 9 Memory Map IO Register
comment ###########################################
setmem 0xCC800000 0x0000 16

comment ### PCCR0 (Set HCLK_LCDC_EN)
setmem 0x10027020 0x35084003 32

comment ###########################################
comment ## Init LCDC 
comment ###########################################

comment ###############
comment ## IO Port
comment ###############

comment ## Clear Port A for LCD signals
comment Port A PTA_GIUS
setmem 0x10015020 0x00000000 32
comment Port A PTA_GPR
setmem 0x10015038 0x00000000 32

comment #######################
comment ## LCDC Configuartion
comment #######################

comment ### Screen Starting Address Register
comment # Point to SDRAM
setmem 0x10021000 0xC2000000 32

comment ### Size Register
setmem 0x10021004 0x00F00140 32

comment ### Virtual Page Width
setmem 0x10021008 0x00000078 32

comment ### Cursor
setmem 0x1002100C 0x40010001 32
setmem 0x10021010 0x1F1F0000 32
setmem 0x10021014 0x0000F800 32

comment ### Cursor OFF
comment ### setmem 0x1002100C 0x00000000 32

comment ### Panel Configuration Register

comment ## 18-bpp
comment setmem 0x10021018 0xFD148BC7 32
comment ## 16-bpp
setmem 0x10021018 0xFB148BC7 32

comment ### Sharp Configuration Register
setmem 0x10021028 0x00120300 32

comment hsyn width = 12  hsyn_wait 1 = 15 hsyn_wait2 = 15
setmem 0x1002101C 0x04000F06, 32

comment vsyn width = 1  vsyn_wait 1 = 0 vsyn_wait2 = 4
setmem 0x10021020 0x04000907, 32

comment LPCCR Register (Set CLS_HI_WIDTH) without backlight
comment setmem 0x1002102C 0x00A90200, 32
comment LPCCR Register (Set CLS_HI_WIDTH) with backlight
setmem 0x1002102C 0x00A903FF, 32

comment Refresh Mode Control Register
setmem 0x10021034 0x00000000, 32

comment ### LDCR Register (LCDC DMA)
setmem 0x10021030 0x00020008, 32

comment ### Enable LCDC
comment ### HCLK_LCDC_EN = 1 and LCDC_PIXCLK_EN = 1
comment ### PCCR0
setmem 0x10027020 0x350C4003 32

comment ###########################################
comment # LCD ON by bit 9 Memory Map IO Register
comment ###########################################
setmem 0xCC800000 0x200 16

comment ############################################################################
comment ###
comment ### PLL and Clock Setting
comment ###
comment ############################################################################

comment #####################################
comment # CLKO Select
comment #####################################
comment ## CCSR (Set CLKO_SEL = CLK32)
setmem 0x10027028 0x00000300 32
comment ## CCSR (Set CLKO_SEL = FCLK)
comment setmem 0x10027028 0x00000307 32
comment ## CCSR (Set CLKO_SEL = HCLK)
setmem 0x10027028 0x00000308 32

comment ###### MPCTL0: (For 32.768KHz Input Frequency)
comment #      MPLL = 266MHz
comment setmem 0x10027004 0x007B1C73 32

comment #### Select the Frequency
comment ### CSCR: FCLK=MPLL/1; HCLK=FCLK/2; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=133MHz)
comment ### setmem 0x10027000 0x17000607 32
comment ### CSCR: FCLK=MPLL/1; HCLK=FCLK/3; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=88MHz)
comment ##  setmem 0x10027000 0x17000A07 32
comment ### CSCR: FCLK=MPLL/1; HCLK=FCLK/4; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=66MHz)
setmem 0x10027000 0x17000E07 32
comment ### CSCR: FCLK=MPLL/1; HCLK=FCLK/8; #####(If MPLL==266MHz, FCLK=266MHz and HCLK=33MHz)
comment ##  setmem 0x10027000 0x17001E07 32

comment maximize drive strength of address, data, and control signals
comment setmem 0x10027824 0x7FFF7FFF 32
comment setmem 0x10027828 0x7FFF7FFF 32
comment setmem 0x1002782C 0x7FFF7FFF 32
comment setmem 0x10027830 0x7FFF7FFF 32
comment setmem 0x10027834 0x7FFF7FFF 32
comment setmem 0x10027838 0x7FFF7FFF 32
comment setmem 0x1002783C 0x7FFF7FFF 32
comment setmem 0x10027840 0x7FC07FF8 32
comment setmem 0x10027844 0x7FFF7FFF 32
comment setmem 0x10027848 0x7FFF7FFF 32
comment lb "D:\cygwin\src\ecos\install\bin\redboot.bin", 0xC2000000