init_ddr.inc

Redboot, boot-loader of Linux for Freescale ARM family.

wait = on


// SPBA setup
setmem /32 0x5003C004 =0x7
setmem /32 0x5003C00C =0x7
setmem /32 0x5003C010 =0x7
setmem /32 0x5003C014 =0x7
setmem /32 0x5003C018 =0x7
setmem /32 0x5003C01C =0x7
setmem /32 0x5003C024 =0x7
setmem /32 0x5003C028 =0x7
setmem /32 0x5003C040 =0x7
setmem /32 0x5003C044 =0x7
setmem /32 0x5003C048 =0x7
setmem /32 0x5003C04C =0x7
setmem /32 0x5003C050 =0x7
setmem /32 0x5003C054 =0x7
setmem /32 0x5003C058 =0x7
setmem /32 0x5003C05C =0x7

; -----------------------------
; Make CKOH controlled by CKOH
; -----------------------------
setmem /16 0x50040016 = 0x0000

; --------------------------------------------------------------
; Initialize DDR SDRAM 
; --------------------------------------------------------------

; Configure Enhanced SDRAM Miscellaneous Register (ESDMISC) Register
; Set to DDR Mode (Not SDR), Do a delay line reset
; as the EMI AHB clock was changed
setmem /32 0xB8001010 =0x0000000c 

; Wait for some time for Delay line to lock
pause 1

; Configure Enhanced SDRAM Configuration Register 0 (ESDCFG0) Register
; XP=2 MRD=2 RAS=6 CAS=3 Clocks
setmem /32 0xB8001004 =0x00395728 


;****************************************************
; The following sequence is required to startup DDRAM
; Do NOT modify or rearrange please
;****************************************************

; Precharge all rows (ROW/COL Muxing NOT used outside NORMAL Mode)
; MODE=PRECHARGE ALL.
setmem /32 0xB8001000 =0x92210080 
; PRECHARGE ALL (A10=1). 
setmem /16 0x80000400 =0x0000     

; Run two refresh cycles
; MODE=AUTO REFRESH
setmem /32 0xB8001000 =0xA2210080 
; AUTO REFRESH
setmem /16 0x80000000 =0x0000
; AUTO REFRESH     
setmem /16 0x80000000 =0x0000     

; Configure DDRAM Operating mode to Load Mode Register Command
; MODE=LOAD MODE REGISTER.
setmem /32 0xB8001000 =0xB2210080 
; LOAD MODE
setmem /8  0x80000033 =0x00	 
; Load Extended Mode register
setmem /16 0x81000000 =0x0000	

; Put controller in Normal mode. SDRAM now ready for accesses
; Configure CSD0 ESDCTL0 and go into Normal Read/Write Mode
; 16-bit[D0..D15];  BL=8; row=13; col=10; MODE=Normal 
setmem /32 0xB8001000 =0x82216080
 ; Dummy Write 
setmem /16 0x80000000 =0x0000    

; Dummy write into DDRAM
setmem /32 0x80000000 =0xC001C001 

; Dummy Read From DDRAM 
dump /32 0x80000000

;; DISABLE CSD1
setmem /32 0xB8001008 =0x00000000
; ----------------------------
; End of DDRAM initialization 
; ----------------------------

; --------------------------------------------------------------
; Initialize WEIM CS0 setup (A-Sync. Mode)
; --------------------------------------------------------------

; Configure CS0 UCR for operation at 133MHz  
; NO Burst Enabled (A-Sync. Mode) 133MHz 
setmem /32 0xB8002000 =0x0000CC03    

; Configure CS0 LCR

setmem /32 0xB8002004 =0xA0330D01   

; Configure CS0 ACR

setmem /32 0xB8002008 =0x00220800 

;--------------------------------------------------------------
; CS4 PSRAM in Async mode setup
; --------------------------------------------------------------

; Configure CS4 UCR for EVB x16 CPLD and PSRAM for operation at 133MHz(lightly padded)

; Configure CS4 UCR
setmem /32 0xB8002040 =0x0000DCF6  

; Configure CS4 LCR
setmem /32 0xB8002044 =0x444A4541  

; Configure CS4 ACR
setmem /32 0xB8002048 =0x44443302  

; PSRAM Initialization completed  

readfile,raw,gui "X:\redboot\build\mxc91221evbROMRAM\install\bin\redboot.bin"=0x83f00000
setreg @R15=0x83F00000