init_ddr.inc

Redboot, boot-loader of Linux for Freescale ARM family.

clearbreak
bexec 0x00000000
wait = on
reset
pause 1

setreg @CP15_CONTROL=0x00050078
// configuring CP15 for enabling the pripheral bus
setreg @CP15_PERIP_MEM_REMAP=0x40000015

// This starts a comment line
// SPBA setup
setmem /32 0x5003C00C =0x7
setmem /32 0x5003C01C =0x7
setmem /32 0x5003C024 =0x7
setmem /32 0x5003C028 =0x7
setmem /32 0x5003C040 =0x7
setmem /32 0x5003C044 =0x7
setmem /32 0x5003C048 =0x7
setmem /32 0x5003C04C =0x7
setmem /32 0x5003C050 =0x7
setmem /32 0x5003C054 =0x7
setmem /32 0x5003C058 =0x7
setmem /32 0x5003C05C =0x7

// Drive strength setup
setmem /16 0x50040200 =0x0092 
setmem /16 0x50040202 =0x0002  
setmem /16 0x50040204 =0x0102 
setmem /16 0x50040206 =0x0092 
setmem /16 0x50040208 =0x0103 
setmem /16 0x5004020a =0x01c3 
setmem /16 0x5004020c =0x0183 
setmem /16 0x50040210 =0x0103 
setmem /16 0x50040212 =0x0183 
	
// WEIM manual reset
setmem /32 0xB8002000 =0x00001E00
setmem /32 0xB8002004 =0x20000D01
setmem /32 0xB8002008 =0

; reset delay line required as the pll freq. changed 
setmem /32 0xb8001010 =0x0000000c 
pause 2

setmem /32 0xB8001004 =0x0079E7BA  
setmem /32 0xB8001010 =0x00000004  


setmem /32 0xB8001000 =0x92216080  
setmem /8  0x80000400 =0x00  
setmem /32 0xB8001000 =0xA2216080  
setmem /8  0x80000000 =0x00  
setmem /8  0x80000000 =0x00  
setmem /32 0xB8001000 =0xB2216080  
setmem /8  0x80000033 =0x00  
setmem /8  0x81000000 =0x00  
setmem /32 0xB8001000 =0x82216080  
setmem /8  0x80000000 =0x00  


;// Dummy write into DDRAM
setmem /32 0x80000000 =0xc001c001 
;// Dummy read from DDR
dump /32 0x80000000
// enable IPU clock
setmem /32 0x50048020 =0x471C4924
setmem /32 0x50048034 =0x41244924

readfile,raw,gui "r:\tftp\mxc27530evb_redboot.bin"=0x81f00000
setreg @R15=0x81F00000