vanilla_skye_p0a_v03_dsp.cfg

Redboot, boot-loader of Linux for Freescale ARM family.

;*======================================================================
;* Copyright (C) 2007, Freescale Semiconductor, Inc. All Rights Reserved
;* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
;* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
;* Freescale Semiconductor, Inc.
;*======================================================================
; Initialization script for MXC300-31_SKYE board using CW MXC.
;*================================================================================================
; Revision History:
;                             Modification     Tracking
; Author (core ID)             Date D/M/Y       Number    Description of Changes
; -------------------------   ------------    ----------  ----------------------------------------
; Chris Lebouc (r70103c)       07/08/2006     TLSbo71942  Creation of the file.
; Costea Bogdan (r89891)       25/04/2007     ENGR36871   Applying Skye ICD 02.00
; Vincent Nurit/Fabrice Sorel (r58755/r58792) 15/05/2007  V02 : Updates at end of bringup. 	  
; Vincent Nurit/Mukesh Bansal (r58792/r62341) 30/05/2007  V03 : Updates on CSD1 timings, forcing delay lines measurement, and PLL init order
;*================================================================================================

; Set JTAG speed to 1 Mhz pre-reset. After reset, the JTAG clock speed will
; be changed according to the value provided in the "Remote Debugging" Panel.
PRE-RESET-ON
DSPJTAGClockSpeed 1000
PRE-RESET-OFF

POST-RESET-ON

; Disable external interrupts
writemem32 0xFFF00540 0x00000000
writemem32 0xFFF00544 0x00000000
writemem32 0xFFF00548 0x00000000
writemem32 0xFFF0054C 0x00000000

; Grant IOMUX SPBA
writemem32 0x5003C040 0x00000007

; set_dual_pll_166MHz clock from Vinz Tcl 
; PLLAP (166MHz) --> EMI (166MHz)
; PLLBP (532MHz) --> DSP (266MHz) + MCU (399MHz)
; set_bp clock from Vinz Tcl 
writemem32 0xFFFC8000 0x00000000
writemem32 0xFFFC8004 0x00000001
writemem32 0xFFFC8008 0x00130309
writemem32 0xFFFC800C 0x00000FFF
;  set_pllap_166MHz  from Vinz Tcl 
;  Set PLL AP to 166MHz.
writemem32 0x5004C004 0x00000002
writemem32 0x5004C008 0x00000061 
writemem32 0x5004C00C 0x00000103  
writemem32 0x5004C010 0x00000064   
writemem32 0x5004C01C 0x00000061  
writemem32 0x5004C020 0x00000103   
writemem32 0x5004C024 0x00000064   
writemem32 0x5004C028 0x00020000
writemem32 0x5004C000 0x00000033

; Initializing AP side clocks."
writemem32 0x50048000 0x00000083
writemem32 0x50048004 0x00000005
writemem32 0x50048008 0x00010211
writemem32 0x5004800C 0x5C472C2C
writemem32 0x50048010 0x7777E6F6
writemem32 0x50048014 0x00000007

; delay line setting for Write - offset = 0 instead of -3(default)
writemem32 0x50075030 0x00000000

; MCP_init_166 Vinz inits 05/10/07
writemem32 0x50075014 0x00008000
writemem32 0x50075000 0x82120000      
writemem32 0x50075004 0x992967a9 
; Force delay line measurement
writemem32 0x50075010 0x00000c84  
writemem32 0x50075010 0x00000684  
writemem32 0x50075014 0x04008008
writemem32 0x50075014 0x00008010
writemem32 0x50075014 0x00008010
writemem32 0x50075014 0x00338018
writemem32 0x50075014 0x0000801A
writemem32 0x50075014 0x00008000
writemem32 0x50075000 0x82128000      
writemem32 0x50075014 0x00000000

; MCP DDR 166 MHz simple write testing
writemem32 0x80000000 0xDEADBEEF
writemem32 0x80000004 0xC001DEAD
writemem32 0x80000008 0xDEADC001
writemem32 0x8000000C 0xFFFFFFFF
writemem32 0x80000010 0x55555555
writemem32 0x80000014 0xAAAAAAAA
writemem32 0x80000018 0x00000000


; DIS_init_166 Vinz inits 05/10/07
writemem32 0x50075014 0x00008004
writemem32 0x50075008 0x82120000
writemem32 0x5007500C 0x208967a9
writemem32 0x50075010 0x00000684  
writemem32 0x50075014 0x0400800C
writemem32 0x50075014 0x00008014
writemem32 0x50075014 0x00008014
writemem32 0x50075014 0x0033801C  
writemem32 0x50075014 0x0000801E
writemem32 0x50075014 0x00008004
writemem32 0x50075008 0x82128000
writemem32 0x50075014 0x00000004

; Discrete DDR 166 MHz simple write testing
writemem32 0x90000000 0xDEADBEEF
writemem32 0x90000004 0xC001DEAD
writemem32 0x90000008 0xDEADC001
writemem32 0x9000000C 0xFFFFFFFF
writemem32 0x90000010 0x55555555
writemem32 0x90000014 0xAAAAAAAA
writemem32 0x90000018 0x00000000