📄 init_ddr.inc
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wait = onsetreg @CP15_CONTROL=0x00050078// SPBA setupsetmem /32 0x5003C000 =0x7setmem /32 0x5003C004 =0x7setmem /32 0x5003C008 =0x7setmem /32 0x5003C00C =0x7setmem /32 0x5003C010 =0x7setmem /32 0x5003C014 =0x7setmem /32 0x5003C018 =0x7setmem /32 0x5003C01C =0x7setmem /32 0x5003C020 =0x7setmem /32 0x5003C024 =0x7setmem /32 0x5003C028 =0x7setmem /32 0x5003C02C =0x7setmem /32 0x5003C030 =0x7setmem /32 0x5003C034 =0x7setmem /32 0x5003C038 =0x7;*================================================================================================; Drive Strength Initialization ;*================================================================================================; max drive strength for all pads except SDQS0/1;*================================================================================================; This Task is done in IOMUX_CTL;*================================================================================================; set_drive_strenght_ctl_signals;*================================================================================================;sw_pad_ctl_dqm1_oe_b_cs0_bsetmem /32 0x500002FC =0x00001800 ;sw_pad_ctl_ctl_eb1_b_eb2_b_dqm0setmem /32 0x50000300 =0x00000007;*================================================================================================; set_drive_strength_ctl_data;*================================================================================================;sw_pad_ctl_sd0_sd1_sd2setmem /32 0x50000318 =0x00700000;*================================================================================================; set_drive_strength_ctl_addr;*================================================================================================;sw_pad_ctl_a0_ma0_a1_ma1_a2_ma2setmem /32 0x5000033C =0x00700000;sw_pad_ctl_RASsetmem /32 0x500002E8 =0x00700000;sw_pad_ctl_SDCLKsetmem /32 0x500002E4 =0x00001C00;for SDRAM SDQS0 lines */setmem /32 0x50000304 =0x00001C00pause 1;*================================================================================================; Drive strength initialization done !;*================================================================================================; --------------------------------------------------------; DDRAM Initialization (ESDCTL-CSD0); This is the MDDR Delay Line 5 Config Debug register (Chapter 35.3.3.6); This controls the data bus write cycles, the delay is 62 inverters.; --------------------------------------------------------;###DDRAM Delay Register;#;#Default Setting;setmem /32 0xB8001030 0x001C0000;#;#Optimized Settingsetmem /32 0xB8001030 =0x003E0000; ================================================================================; ------ Configure DDRAM Chip Select (CSD0) for 133 MHz operation ----------------; -------------------- FOR x16 DDR [D0..D15] -------------------------------; This sequence initializes the PISMO memory card which has an Infineon; HY18M512160AF 512-Mbit density, 16-bit bus DDR Mobile DRAM; --------------------------------------------------------------------------------; Configure CSD0 ESDCFG0 ; 4 clk delay before new cmd, 2clk write to read cmd delay, 3clk row precharge delay, ; 2 clk idle between load-mode-reg cmd to Active cmd setmem /32 0xB8001004 =0x0079E73A; Configure ESDMISC Enable MDDR and Measurement Unit; MA10 share disable, latency hiding enabled, LPDDR delay line measure enable, LPDDR delay line not reset; enable DDR operation, soft reset disabled, mddr_en normal operation; Set to DDR Modesetmem /32 0xB8001010 =0x00000004pause 1; Configure SDRAM Operating mode to Precharge Command ; Configure ESCDTL0 - enable controller, normal r/w, user mode access prohibited; 13 row addresses,10 col,16bit[d15:0]; 4 rows/refresh clk,8192 rows/64ms, pwdn disabled,no page burst,burst length=8,precharge timer disabled ; 133MHz; 16-bit[D0..D15]; BL=8; row=13; col=10; MODE=PRECHARGE ALL.setmem /32 0xB8001000 =0x92216080; Set A10 to issue precharge all command.; PRECHARGE ALL (A10=1). ROW/COL Muxing NOT used outside NORMAL Mode.setmem /16 0x80000400 =0x0000; Configure SDRAM Operating mode to Auto-Refresh Command ;133MHz; 16-bit[D0..D15]; BL=8; row=13; col=10; MODE=AUTO REFRESHsetmem /32 0xB8001000 =0xA2216080; CSD0 SDRAM Base Addr (2 auto-refresh commands)setmem /16 0x80000000 =0x0000setmem /16 0x80000000 =0x0000; Configure SDRAM Operating mode to Load Mode Register Command; 133MHz; 16-bit[D0..D15]; BL=8; row=13; col=10; MODE=LODE MODE REGISTER.setmem /32 0xB8001000 =0xB2216080; Value to write to DDR mode register is entered through Address Bus; BL=8, BT=Seq., CAS=3 (Program MODE REGISTER)setmem /8 0x80000033 =0x00; Write extended mode register - Bank Addresses BA1-0 at addr A25-24 respectively; Self Refresh Coverage = 4 Banks, Driver Strength = Full strength. (Program MODE EXTENDED REGISTER, (BA1/A24=1).)setmem /16 0x81000000 =0x0000; Configure CSD0 ESDCTL0 and go into Normal Read/Write Mode; enable SDRAM controller, 13 row addr, 10 colm,d[15:0]-16bit, 4 rows/refresh clk, run mode,no page burst,; burst length=8, ; 133MHz; 16-bit[D0..D15]; BL=8; row=13; col=10; MODE=Normal. setmem /32 0xB8001000 =0x82216080; Dummy Write.setmem /16 0x80000000 =0x0000; ------------------------- END CONFIGURE DDRRAM --------------------------------------------; ==============================================================================================; --------------------------------------------------------------; Configure AP Clocks ARM:AHB:IP= 266MHz:66MHz:66.5MHz; --------------------------------------------------------------setmem /32 0x53F80004 =0xFF800418;setmem /32 0x53F80004 =0xFF800448setmem /32 0x53F80044 =0x819F3180; ==============================================================; Initialize WEIM CS0 setup - WEIM Chapter; Need to set chip select upper/lower/additional control registers; --------------------------------------------------------------; Configure CS0 UCR for operation at 133MHz ; allow user access,allow writes, ;3 AHB cls CS negated,19 wait states,terminate burst mode,4 write wait states,6 extra dead cycles; NO Burst Enabled (A-Sync. Mode) setmem /32 0xB8002000 =0x0000D346; Configure CS0 LCR; 2clk oe assert,2clk oe negate,2clk eb assert,2clk eb negate,2clk cs assert,; enable write byte ctl,16bit port d15-d0,1clk cs negate,PSR=0,CRE=0,Wrap mode off,CS0 enablesetmem /32 0xB8002004 =0x444A4D21; Configure CS0 ACR; 2clk eb read assert,2clk eb read negate, 2clk rw assert, 2clk rw negate,; non-mux mode, 6.5clk between LBA negate to addr invalid, 2clk LBA negate, 1.5clk LBA assert,; 2clk between cs assert and first dtack, prevent wrap during write, disable ack glue logic,8 clk cycle cs negatesetmem /32 0xB8002008 =0x44443302; ==============================================================; CS4 setup for CPLD and PSRAM; --------------------------------------------------------------; Configure CS4 UCR for EVB x16 CPLD and PSRAM for operation at 133MHz; 3 AHB cls CS negated,28 wait states,terminate burst mode,ECB wait,7+28 write wait states,6 extra dead cyclessetmem /32 0xB8002040 =0x0000DCF6; Configure CS4 LCR; 2clk oe assert,2clk oe negate,2clk eb assert,2clk eb negate,2clk cs assert,; enable r/w byte ctl,16bit port d15-d0,2clk cs negate,PSR=0,CRE=0,Wrap mode off,CS4 enablesetmem /32 0xB8002044 =0x444A4541; Configure CS4 ACR; 2clk eb read assert,2clk eb read negate, 2clk rw assert, 2clk rw negate,; non-mux mode, 6.5clk between LBA negate to addr invalid, 2clk LBA negate, 1.5clk LBA assert,; 2clk between cs assert and first dtack, prevent wrap during write, disable ack glue logic,8 clk cycle cs negatesetmem /32 0xB8002048 =0x44443302; PSRAM Initialization completed ; ---------------------------------------------------------------setmem /32 0x5001C808 =0x00000000 // Set DSP to LEsetmem /32 0x43F84024 =0x00000010 // Put DSP in resetpause 1setmem /32 0x43F84024 =0x00000000 // Put DSP out of resetsetreg @CPSR_FLGE=0x00readfile,raw,gui "D:\LINUX\BOOTLOADERS\REDBOOT\bin\mxc30020evb_redboot.bin"=0x83F00000setreg @R15=0x83F00000⌨️ 快捷键说明
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