📄 opb_lcd_interface.vhd
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--***********************************************************************************
--* File Name: opb_lcd_interface.vhd
--* Version: 1.00
--* Date: Oct 25, 2002
--* File Hierarchy: Top Level Module
--* Dependencies: lcd_interface_core.vhd, ipif.vhd
--*
--* Designer: Nasser Poureh
--* Company: Insight Electronics
--*
--*
--* Description: This is the opb_lcd_interface top-level design.
--*
--************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_a;
library opb_ipif_v1_23_a;
use proc_common_v1_00_a.all;
use opb_ipif_v1_23_a.all;
-- The opb_lcd_interface module contains 4 generics that will be used in a design MHS file
-- for mapping the core into the processor memory map (via C_BASEADDR and C_HIGHADDR) and
-- also defining the width of the OPB address and data buses used by the core (default to
-- 32 for both address and data bus).
entity opb_lcd_interface is
generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF7000";
C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFF7FFF"
);
port (
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_DBus : in std_logic_vector(0 to 31);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
LCD_INTERFACE_DBus : out std_logic_vector(0 to 31);
LCD_INTERFACE_errAck : out std_logic;
LCD_INTERFACE_retry : out std_logic;
LCD_INTERFACE_toutSup : out std_logic;
LCD_INTERFACE_xferAck : out std_logic;
lcd_data : out std_logic_vector (0 to 7);
lcd_en : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
end opb_lcd_interface;
architecture opb_lcd_interface_arch of opb_lcd_interface is
-- This following function calculates the number of address bits that are needed to generating
-- chip select for the lcd interface by the ipif. This function takes the lcd core base address
-- and the lcd core high address and returns an integer that corresponds to the number bits
-- needed. For this design, the number bits needed is assigned to a constant called C_AB.
function Addr_Bits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_OPB_AWIDTH-1 loop
if addr_nor(i) = '1' then return i;
end if;
end loop;
return(C_OPB_AWIDTH);
end function Addr_Bits;
constant C_AB : integer := Addr_Bits(C_HIGHADDR, C_BASEADDR);
-- lcd core components or could call it user ip.
component lcd_interface_core
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_Reg_WrCE : in std_logic_vector(0 to 0);
Bus2IP_Reg_RdCE : in std_logic_vector(0 to 0);
Bus2IP_Data : in std_logic_vector (0 to 31);
IP2Bus_Data : out std_logic_vector (0 to 31);
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
lcd_data : out std_logic_vector (0 to 7);
lcd_en : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
end component;
-- ipif component.
component ipif
generic (
C_DEV_BLK_ID : INTEGER := 0;
C_DEV_MIR_ENABLE : BOOLEAN := False;
C_DEV_BASEADDR : std_logic_vector := X"FFFF_7000";
C_OPB_ABUS_WIDTH : INTEGER := 32;
C_OPB_DBUS_WIDTH : INTEGER := 32;
C_OPB_BE_NUM : INTEGER := 4;
C_DEV_BURST_ENABLE : BOOLEAN := False;
C_DEV_MAX_BURST_SIZE : INTEGER := 64;
C_RESET_PRESENT : BOOLEAN := False;
C_INTERRUPT_PRESENT : BOOLEAN := True;
C_INCLUDE_DEV_PENCODER : BOOLEAN := False;
C_IP_MASTER_PRESENT : BOOLEAN := False;
C_IP_REG_PRESENT : BOOLEAN := True;
C_IP_REG_NUM : INTEGER := 3;
C_IP_IRPT_NUM : INTEGER := 1;
C_IP_SRAM_PRESENT : BOOLEAN := False;
C_IP_SRAM_BASEADDR_OFFSET : std_logic_vector := X"00001000";
C_IP_SRAM_SIZE : INTEGER := 256;
C_WRFIFO_PRESENT : BOOLEAN := False;
C_WRFIFO_BASEADDR_OFFSET : std_logic_vector := X"00002100";
C_WRFIFO_REG_BASEADDR_OFFSET : std_logic_vector := X"00002000";
C_RDFIFO_PRESENT : BOOLEAN := False;
C_RDFIFO_BASEADDR_OFFSET : std_logic_vector := X"00002200";
C_RDFIFO_REG_BASEADDR_OFFSET : std_logic_vector := X"00002010";
C_DMA_PRESENT : BOOLEAN := False;
C_DMA_REG_BASEADDR_OFFSET : std_logic_vector := X"00002300";
C_DMA_CHAN_NUM : INTEGER := 2;
C_DMA_CH1_TYPE : INTEGER := 2;
C_DMA_CH2_TYPE : INTEGER := 3;
C_DMA_ALLOW_BURST : BOOLEAN := False;
C_DMA_LENGTH_WIDTH : INTEGER := 11;
C_DMA_INTR_COALESCE : BOOLEAN := False;
C_DMA_PACKET_WAIT_UNIT_NS : INTEGER := 1000000;
C_DMA_TXL_FIFO_IPCE : INTEGER := 8;
C_DMA_TXS_FIFO_IPCE : INTEGER := 9;
C_DMA_RXL_FIFO_IPCE : INTEGER := 7;
C_DMA_RXS_FIFO_IPCE : INTEGER := 15;
C_OPB_CLK_PERIOD_PS : INTEGER := 10000;
C_IP_REG_BASEADDR_OFFSET : std_logic_vector := X"00000100";
C_DEV_ADDR_DECODE_WIDTH : INTEGER := 24;
C_IPIF_ABUS_WIDTH : INTEGER := 4;
C_IPIF_DBUS_WIDTH : INTEGER := 32;
C_VIRTEX_II : Boolean := True;
C_INCLUDE_DEV_ISC : Boolean := False
);
port (
OPB_ABus :in std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1);
OPB_DBus :in std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1);
Sln_DBus :out std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1);
Mn_ABus :out std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1);
IP2Bus_Addr :in std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1);
Bus2IP_Addr :out std_logic_vector(0 to C_IPIF_ABUS_WIDTH - 1);
Bus2IP_Data :out std_logic_vector(0 to C_IPIF_DBUS_WIDTH - 1);
Bus2IP_Reg_RdCE :out std_logic_vector(0 to C_IP_REG_NUM - 1);
Bus2IP_Reg_WrCE :out std_logic_vector(0 to C_IP_REG_NUM - 1);
Bus2IP_SRAM_CE :out std_logic;
IP2Bus_Data :in std_logic_vector(0 to C_IPIF_DBUS_WIDTH - 1);
IP2Bus_WrAck :in std_logic;
IP2Bus_RdAck :in std_logic;
IP2Bus_Retry :in std_logic;
IP2Bus_Error :in std_logic;
IP2Bus_ToutSup :in std_logic;
IP2DMA_RxLength_Empty :in std_logic;
IP2DMA_RxStatus_Empty :in std_logic;
IP2DMA_TxLength_Full :in std_logic;
IP2DMA_TxStatus_Empty :in std_logic;
IP2IP_Addr :in std_logic_vector(0 to C_IPIF_ABUS_WIDTH - 1);
IP2RFIFO_Data :in std_logic_vector(0 to 31);
IP2RFIFO_WrMark :in std_logic;
IP2RFIFO_WrRelease :in std_logic;
IP2RFIFO_WrReq :in std_logic;
IP2RFIFO_WrRestore :in std_logic;
IP2WFIFO_RdMark :in std_logic;
IP2WFIFO_RdRelease :in std_logic;
IP2WFIFO_RdReq :in std_logic;
IP2WFIFO_RdRestore :in std_logic;
IP2Bus_MstBE :in std_logic_vector(0 to C_OPB_BE_NUM - 1);
IP2Bus_MstWrReq :in std_logic;
IP2Bus_MstRdReq :in std_logic;
IP2Bus_MstBurst :in std_logic;
IP2Bus_MstBusLock :in std_logic;
Bus2IP_MstWrAck :out std_logic;
Bus2IP_MstRdAck :out std_logic;
Bus2IP_MstRetry :out std_logic;
Bus2IP_MstError :out std_logic;
Bus2IP_MstTimeOut :out std_logic;
Bus2IP_MstLastAck :out std_logic;
Bus2IP_BE :out std_logic_vector(0 to C_OPB_BE_NUM - 1);
Bus2IP_WrReq :out std_logic;
Bus2IP_RdReq :out std_logic;
Bus2IP_Burst :out std_logic;
Mn_request :out std_logic;
Mn_busLock :out std_logic;
Mn_select :out std_logic;
Mn_RNW :out std_logic;
Mn_BE :out std_logic_vector(0 to C_OPB_BE_NUM - 1);
Mn_seqAddr :out std_logic;
OPB_MnGrant :in std_logic;
OPB_xferAck :in std_logic;
OPB_errAck :in std_logic;
OPB_retry :in std_logic;
OPB_timeout :in std_logic;
Freeze :in std_logic;
RFIFO2IP_AlmostFull :out std_logic;
RFIFO2IP_Full :out std_logic;
RFIFO2IP_Vacancy :out std_logic_vector(0 to 9 );
RFIFO2IP_WrAck :out std_logic;
OPB_select :in std_logic;
OPB_RNW :in std_logic;
OPB_seqAddr :in std_logic;
OPB_BE :in std_logic_vector(0 to C_OPB_BE_NUM - 1);
Sln_xferAck :out std_logic;
Sln_errAck :out std_logic;
Sln_toutSup :out std_logic;
Sln_retry :out std_logic;
WFIFO2IP_AlmostEmpty :out std_logic;
WFIFO2IP_Data :out std_logic_vector(0 to 31 );
WFIFO2IP_Empty :out std_logic;
WFIFO2IP_Occupancy :out std_logic_vector(0 to 9 );
WFIFO2IP_RdAck :out std_logic;
Bus2IP_Clk :out std_logic;
Bus2IP_DMA_Ack :out std_logic;
Bus2IP_Freeze :out std_logic;
Bus2IP_Reset :out std_logic;
IP2Bus_Clk :in std_logic;
IP2Bus_DMA_Req :in std_logic;
IP2Bus_IntrEvent :in std_logic_vector(0 to C_IP_IRPT_NUM - 1);
IP2INTC_Irpt :out std_logic;
OPBClk :in std_logic;
Reset :in std_logic
);
end component;
signal Bus2IP_Data : std_logic_vector (0 to 31);
signal IP2Bus_Data : std_logic_vector (0 to 31);
signal IP2Bus_WrAck : std_logic;
signal IP2Bus_RdAck : std_logic;
signal Bus2IP_WrReq : std_logic;
signal Bus2IP_RdReq : std_logic;
signal Bus2IP_Clk : std_logic;
signal Bus2IP_Reset : std_logic;
signal Bus2IP_Reg_RdCE : std_logic_vector(0 to 0);
signal Bus2IP_Reg_WrCE : std_logic_vector(0 to 0);
begin
-- Port mapping of the ipif component for the lcd application. The mapping of the vhdl generics
-- indicates that the ipif register type access is used to interface to the lcd panel (all other
-- access types are set to false).
opb_lcd_ipif: ipif
generic map (
C_DEV_BLK_ID => 0,
C_DEV_MIR_ENABLE => False,
C_OPB_BE_NUM => 4,
C_DEV_MAX_BURST_SIZE => 64,
C_IP_IRPT_NUM => 1,
C_IP_SRAM_BASEADDR_OFFSET => X"00001000",
C_IP_SRAM_SIZE => 256,
C_WRFIFO_BASEADDR_OFFSET => X"00002100",
C_WRFIFO_REG_BASEADDR_OFFSET => X"00002000",
C_RDFIFO_BASEADDR_OFFSET => X"00002200",
C_RDFIFO_REG_BASEADDR_OFFSET => X"00002010",
C_DMA_REG_BASEADDR_OFFSET => X"00002300",
C_DMA_CHAN_NUM => 2,
C_DMA_CH1_TYPE => 2,
C_DMA_CH2_TYPE => 3,
C_DMA_ALLOW_BURST => False,
C_DMA_LENGTH_WIDTH => 11,
C_DMA_INTR_COALESCE => False,
C_DMA_PACKET_WAIT_UNIT_NS => 1000000,
C_DMA_TXL_FIFO_IPCE => 8,
C_DMA_TXS_FIFO_IPCE => 9,
C_DMA_RXL_FIFO_IPCE => 7,
C_DMA_RXS_FIFO_IPCE => 15,
C_VIRTEX_II => True,
C_DEV_BASEADDR => C_BASEADDR,
C_OPB_ABUS_WIDTH => C_OPB_AWIDTH,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH,
C_DEV_ADDR_DECODE_WIDTH => C_AB,
C_DEV_BURST_ENABLE => False,
C_RESET_PRESENT => False,
C_INTERRUPT_PRESENT => False,
C_INCLUDE_DEV_PENCODER => False,
C_IP_MASTER_PRESENT => False,
C_IP_REG_PRESENT => true,
C_IP_REG_NUM => 1,
C_IP_REG_BASEADDR_OFFSET => X"00000000",
C_IP_SRAM_PRESENT => False,
C_WRFIFO_PRESENT => False,
C_RDFIFO_PRESENT => False,
C_DMA_PRESENT => False,
C_IPIF_ABUS_WIDTH => 4,
C_IPIF_DBUS_WIDTH => 32,
C_INCLUDE_DEV_ISC => False
)
port map (
Reset => OPB_Rst,
OPBClk => OPB_Clk,
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => LCD_INTERFACE_xferAck,
Sln_errAck => LCD_INTERFACE_errAck,
Sln_toutSup => LCD_INTERFACE_toutSup,
Sln_retry => LCD_INTERFACE_retry,
Sln_DBus => LCD_INTERFACE_DBus,
IP2Bus_Clk => OPB_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Addr => open,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_Reg_RdCE => Bus2IP_Reg_RdCE,
Bus2IP_Reg_WrCE => Bus2IP_Reg_WrCE,
Bus2IP_SRAM_CE => open,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2RFIFO_Data => X"00000000",
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => X"0",
IP2Bus_MstWrReq => '0',
IP2Bus_MstRdReq => '0',
IP2Bus_MstBurst => '0',
IP2Bus_MstBusLock => '0',
OPB_MnGrant => '0',
OPB_xferAck => '0',
OPB_errAck => '0',
OPB_retry => '0',
OPB_timeout => '0',
Freeze => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => X"0",
IP2Bus_Data => IP2Bus_Data,
IP2Bus_Addr => X"00000000",
IP2IP_Addr => X"00000000",
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Retry => '0',
IP2Bus_Error => '0',
IP2Bus_ToutSup => '0',
Bus2IP_BE => open,
Bus2IP_WrReq => Bus2IP_WrReq,
Bus2IP_RdReq => Bus2IP_RdReq
);
u1_lcd_interface_core: lcd_interface_core
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_RdReq => Bus2IP_RdReq,
Bus2IP_WrReq => Bus2IP_WrReq,
Bus2IP_Reg_WrCE => Bus2IP_Reg_WrCE,
Bus2IP_Reg_RdCE => Bus2IP_Reg_RdCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
lcd_data => lcd_data,
lcd_en => lcd_en,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw
);
end opb_lcd_interface_arch;
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