lcd_interface_core.vhd

基于MicroBlaze软处理器核的Threadx代码

--***********************************************************************************
--*	     File Name:		lcd_interface_core.vhd
--*	       Version:		1.00
--*		  	  Date:		Oct 25, 2002
--*	File Hierarchy:		Low Level Module
--*	  Dependencies:		None
--*  
--*	      Designer:		Nasser Poureh
--*	       Company:		Insight Electronics
--*
--*
--*	   Description:		This module implements the lcd ip core that interfaces to the
--*						lcd panel on one side and to the user side of the opb ipif on
--*						the other side. Although, the lcd panel supports read access
--*						in addition to write, this core only implements writing to the
--*						lcd. When a read cycle in initiated, the core returns zeros on
--*						the data bus.
--* 			               
--************************************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;



entity lcd_interface_core is
		port	(
    			Bus2IP_Clk 					: in std_logic;
    			Bus2IP_Reset 				: in std_logic;
    			Bus2IP_RdReq  				: in std_logic;
    			Bus2IP_WrReq     			: in std_logic;
    			Bus2IP_Reg_WrCE    			: in std_logic_vector(0 to 0);
    			Bus2IP_Reg_RdCE    			: in std_logic_vector(0 to 0);
				Bus2IP_Data 				: in std_logic_vector (0 to 31);
				IP2Bus_Data 				: out std_logic_vector (0 to 31);
    			IP2Bus_WrAck  				: out std_logic;        
    			IP2Bus_RdAck   				: out std_logic;        
    			lcd_data		   			: out std_logic_vector (0 to 7);
    			lcd_en 	 					: out std_logic;
	 			lcd_rs	 	 				: out std_logic;
    			lcd_rw			  			: out std_logic
    			);
end lcd_interface_core;



architecture lcd_interface_core_arch of lcd_interface_core is


signal	IP2Bus_WrAck_i				: std_logic;
signal	IP2Bus_RdAck_i				: std_logic;
signal	lcd_control_data 			: std_logic_vector (0 to 9);
signal	ack_count		 			: std_logic_vector (0 to 5);
signal	ack_count_tc		 		: std_logic;


begin



--	The following section implements a 10-bit register called lcd_control_data. The 10
--	least significant bits of the OPB are used to write to this register. The contents
--	of this register are used according to the following rule:
--
--	lcd_control_data(0)		MSB		lcd_rs signal
--	lcd_control_data(1)				lcd_rw signal
--	lcd_control_data(2)				lcd data bit 0
--	lcd_control_data(3)				lcd data bit 1
--	lcd_control_data(4)				lcd data bit 2
--	lcd_control_data(5)				lcd data bit 3
--	lcd_control_data(6)				lcd data bit 4
--	lcd_control_data(7)				lcd data bit 5
--	lcd_control_data(8)				lcd data bit 6
--	lcd_control_data(9)		LSB		lcd data bit 7
--
--	Please keep in mind that lcd data bit 0 is the MSB of the lcd data bus and it must
--	be connected to the bit 7 of the lcd panel on the board.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		lcd_control_data <= (others => '0');
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if ( Bus2IP_WrReq = '1' and Bus2IP_Reg_WrCE(0) = '1') then
			lcd_control_data <= Bus2IP_Data(22 to 31);
		end if;
	end if;
end process;





--	The following implements a 6-bit counter that is used during write cycles to the
--	lcd. At the beginning of the write cycle, the counter is loaded with 0x3f and then
--	it is decremented on every rising edge of the clock. A terminal count called
--	ack_count_tc is generated when the count reaches 0x03.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		ack_count <= (others => '0');
	elsif (Bus2IP_WrReq = '1') then
		ack_count <= (others => '1');
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if (Bus2IP_Reg_WrCE(0) = '1') then
			ack_count <= ack_count - 1;
		end if;
	end if;
end process;


process (ack_count)
begin
	if (ack_count = "000011") then
		ack_count_tc <= '1';
	else
		ack_count_tc <= '0';
	end if;
end process;




--	The following uses the ack_count_tc signal to generate the OPB acknowledge signal
--	for the write cycle.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		IP2Bus_WrAck_i <= '0';
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		IP2Bus_WrAck_i <= ack_count_tc;
	end if;
end process;




--	The following uses the read request from the OPB to generate the OPB acknowledge
--	signal for the read cycle. The core terminates a read cycle in 2 clocks and returns
--	zeros on the data bus.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		IP2Bus_RdAck_i <= '0';
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if (Bus2IP_Reg_RdCE(0) = '1') then
			IP2Bus_RdAck_i <= Bus2IP_RdReq;
		end if;
	end if;
end process;




--	Various lcd interface and ipif user side signals are set in the following section.
--	The MSB of the ack_count counter is used to generate the enable signal (lcd_en) to
--	the lcd panel.

IP2Bus_WrAck 				<= IP2Bus_WrAck_i;
IP2Bus_RdAck 				<= IP2Bus_RdAck_i;
IP2Bus_Data (0 to 31 ) 		<= (others => '0');
lcd_rs						<= lcd_control_data(0);
lcd_rw						<= lcd_control_data(1);
lcd_data					<= lcd_control_data(2 to 9);
lcd_en						<= ack_count(0);



end lcd_interface_core_arch;