clk_gen.vhd

基于MicroBlaze软处理器核的Threadx代码

--**************** Embedded Processor Solutions Workshop ************************
--*          File Name:    clk_gen.vhd
--*            Version:    2.0.0
--*               Date:    Mar 17, 2003
--*     File Hierarchy:    Low level module
--*       Dependencies:    None
--*  
--*            Company:    Memec
--*
--*
--*        Description:    This module takes an incoming clock, routes it through a
--*                        DLL, and divides it by two.
--*                              
--************************************************************************************


library ieee;
use ieee.std_logic_1164.all;


entity clk_gen is
  port (
	sys_clk_raw : in std_logic;
	rst_dll     : in std_logic;
	locked_dll  : out std_logic;
	sys_clk_dll : out std_logic);
end entity clk_gen;


architecture rtl of clk_gen is
  
component CLKDLL
      port (CLKIN, CLKFB, RST: in std_logic;
            CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;

-- Attribute to specify how much the CLKDV divides by
attribute CLKDV_DIVIDE: string;
attribute CLKDV_DIVIDE of U1: label is "2.0";
-- other clkdv values: 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0
 
component BUFG
      port (I : in STD_LOGIC; O : out std_logic);
end component;

signal clkin, clkdv, clk0, clk, rst_int, lock_int : std_logic;  

begin

--Invert reset signal
rst_int <= NOT rst_dll;

-- Send the input clock into DLL and divide
U1: CLKDLL port map (CLKIN => sys_clk_raw, CLKFB => clk, CLKDV => clkdv, RST => rst_int,
                     CLK0 => clk0, LOCKED => lock_int);

-- Put the divided clock onto a global buffer for low-skew
U2: BUFG port map (I => clkdv, O => sys_clk_dll);

-- Also put the feedback clock onto a global buffer for low-skew
U3: BUFG port map (I => clk0, O => clk);

-- Invert the DLL LOCK signal since the LED is low-enabled
-- locked_dll <= NOT lock_int;

locked_dll <= lock_int;

end architecture rtl;