📄 tx_ill.asm
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/**************************************************************************/
/* */
/* Copyright (c) 1996-2004 by Express Logic Inc. */
/* */
/* This software is copyrighted by and is the sole property of Express */
/* Logic, Inc. All rights, title, ownership, or other interests */
/* in the software remain the property of Express Logic, Inc. This */
/* software may only be used in accordance with the corresponding */
/* license agreement. Any unauthorized use, duplication, transmission, */
/* distribution, or disclosure of this software is expressly forbidden. */
/* */
/* This Copyright notice may not be removed or modified without prior */
/* written consent of Express Logic, Inc. */
/* */
/* Express Logic, Inc. reserves the right to modify this software */
/* without notice. */
/* */
/* Express Logic, Inc. */
/* 11423 West Bernardo Court info@expresslogic.com */
/* San Diego, CA 92127 http://www.expresslogic.com */
/* */
/* */
/**************************************************************************/
//
//
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize (INI) */
/** */
/**************************************************************************/
/**************************************************************************/
//
//
//#define TX_SOURCE_CODE
//
//
/* Include necessary system files. */
//
//#include "tx_api.h"
//#include "tx_ini.h"
//#include "tx_thr.h"
//#include "tx_tim.h"
//
//
#include "tx_black.h" /* Include common blackfin definitions */
.extern tx_free_memory; // this is from the LDF file
.extern __tx_thread_system_stack_ptr;
.extern __tx_timer_interrupt;
.extern ___lib_setup_c;
.extern __tx_thread_context_save;
.extern __tx_thread_context_restore;
.extern __tx_initialize_unused_memory;
.extern __tx_thread_schedule;
.extern tx_thread_interrupt_return_level;
.global __tx_core_timer_interrupt;
// Core Timer Registers
#define TCNTL 0xFFE03000 // Core Timer Control Register
#define TPERIOD 0xFFE03004 // Core Timer Period Register
#define TSCALE 0xFFE03008 // Core Timer Scale Register
#define TCOUNT 0xFFE0300C // Core Timer Count Register
// name for the memory mapped address of the interrupt vector table
#define EVT0 0xFFE02000 // Event Vector 0 ESR Address
#define IVBh (EVT0 >> 16)
#define IVBl (EVT0 & 0xFFFF)
#define EVT6 0xFFE02018 // Event Vector 6 ESR Address
#define EVT14 0xFFE02038 // Event Vector 14 ESR Address
#define CORE_TIMER_VECTOR_HIGH (EVT6 >> 16)
#define CORE_TIMER_VECTOR_LOW (EVT6 & 0xFFFF)
#define EVT14_VECTOR_HIGH (EVT14 >> 16)
#define EVT14_VECTOR_LOW (EVT14 & 0xFFFF)
.section program;
.align 2;
//
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level BLACKFIN561/VisualDSP */
/* 4.0 */
/* AUTHOR */
/* */
/* Karl Homer, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 07-15-2005 Karl Homer Initial Version 4.0 */
/* */
/**************************************************************************/
//VOID _tx_initialize_low_level(VOID)
//{
.global __tx_initialize_low_level;
__tx_initialize_low_level:
// Setup Event Vectors and Handlers
P0.H = CORE_TIMER_VECTOR_HIGH; // Core timer vector
P0.L = CORE_TIMER_VECTOR_LOW;
// set up Core timer vector
P1.L = __tx_core_timer_interrupt;
P1.H = __tx_core_timer_interrupt; // Timer Interrupt (Int6)
[P0]= P1;
/* Set up to run scheduler at level 14 for RTI */
P0.H = EVT14_VECTOR_HIGH; // level 14 vector
P0.L = EVT14_VECTOR_LOW;
P1.L = tx_thread_interrupt_return_level;
P1.H = tx_thread_interrupt_return_level;
[P0] = P1; // Vector to level 14
/* Save the system stack pointer. */
// _tx_thread_system_stack_ptr = (VOID_PTR) (SP);
// Save the current System stack to thread stack
P0.L = __tx_thread_system_stack_ptr;
P0.H = __tx_thread_system_stack_ptr;
[P0] = SP;
/* Pickup the first available memory address. */
P0.L = tx_free_memory; // Pickup first available memory
P0.H = tx_free_memory; // address
// /* Save the first available memory address. */
// _tx_initialize_unused_memory = (VOID_PTR) tx_free_memory;
R3 = P0;
R1 = 4; // Pad
R0 = R3 + R1;
BITCLR(R0,0); // Align 0 4-byte boundary
BITCLR(R0,1);
P0.L = __tx_initialize_unused_memory;
P0.H = __tx_initialize_unused_memory;
[P0] = R0; // Save new unused memory mark
/* Setup Timer for periodic interrupts. */
// The core timer is used for the basic timer interrupt.
// The core timer runs at the core clock (CCLK) rate. It includes
// four core memory mapped registers TCNTL, (Timer Control), TCOUNT
// (Timer Count), TPERIOD (Timer Period) and TSCALE (Timer Scale).
// When the timer is enabled by setting the TMREN bit in the TCNTL
// register (bit 1) the TCOUNT register is decremented once every
// TSCALE+1 number of clock cycles. When the value of TCOUNT reaches
// zero, an interrupt is generated and the TINT bit is set in the
// TCNTL register. If the "auto reload" bit (TAUTORLD) in the TCNTL
// register is set, the TCOUNT register is reloaded with the value
// of TPERIOD, and the count down begins again.
// Load the control register (It is a memory mapped address)
P0.L = TCNTL & 0xffff;
P0.H = TCNTL >> 16;
// load it with a 5, active power mode, timer disabled, enable
// auto reload.
R0=0x5 (Z);
[P0] = R0;
// load the timer counter register
P0.l = TCOUNT & 0xffff;
P0.h = TCOUNT >> 16;
// The timer is driven by the core clock. That speed is selectable.
// see switch settings document. The ADDS-BF561-EZLITE board defaults to
// a 300MHZ CCLK.
// 10MS for 300 MHz
R1.L = 0xC6C0;
R1.H = 0x002D;
[P0]=R1;
// load the same value into the period register
P0.L = TPERIOD & 0xffff;
P0.H = TPERIOD >> 16;
[P0]=R1;
// no scaling
P0.L = TSCALE & 0xffff;
P0.H = TSCALE >> 16;
R3 = 0x0000 (Z);
[P0]=R3;
P0.L = TCNTL & 0xffff;
P0.H = TCNTL >> 16;
R4 = 0x0007 (Z);
[P0] = R4; //enable Timer
RTS;
//}
.__tx_initialize_low_level.end:
.type __tx_initialize_low_level,STT_FUNC;
/* Define shells for each of the interrupt vectors. */
.align 4;
__tx_core_timer_interrupt:
LINK LINK_STACK_SIZE;
// top of stack is for stack type
// Only saving the scratch register here for now. Others are for counting place holders.
// [SP+0]=1
// [SP+4]=IMASK
// [SP+8]=P5;
// [SP+12]=P4;
// [SP+16]=P3;
[SP+20] = P2;
[SP+24] = P1;
[SP+28] = P0;
// [SP+32]=R7;
// [SP+36]=R6;
// [SP+40]=R5;
// [SP+44]=R4;
[SP+48] = R3;
[SP+52] = R2;
[SP+56] = R1;
[SP+60] = R0;
R0 = astat;
[SP+64] = R0;
JUMP __tx_timer_interrupt; // no return
.__tx_core_timer_interrupt.end:
.type __tx_core_timer_interrupt,STT_FUNC;
.align 4;
.global __tx_example_interrupt;
__tx_example_interrupt:
LINK LINK_STACK_SIZE;
// top of stack is for stack type
// Only saving the scratch register here for now. Others are for counting place holders.
// [SP+0] = 1
// [SP+4] = IMASK
// [SP+8] = P5;
// [SP+12] = P4;
// [SP+16] = P3;
[SP+20] = P2;
[SP+24] = P1;
[SP+28] =P0;
// [SP+32]=R7;
// [SP+36]=R6;
// [SP+40]=R5;
// [SP+44]=R4;
[SP+48]=R3;
[SP+52]=R2;
[SP+56]=R1;
[SP+60]=R0;
R0 = astat;
[SP+64]=R0;
CALL __tx_thread_context_save;
// [--SP] = RETI; // Use this for nested interrupts
// Call your C ISR HERE !!
// RETI = [SP++]; // Use this for nested interrupts
JUMP __tx_thread_context_restore; // No return
.__tx_example_interrupt.end:
.type __tx_example_interrupt,STT_FUNC;
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