tor2.c

This a SOFTWARE pbx DRIVER

		printk("Did not get DONE signal. Short file maybe??\n");
		goto err_out_release_all;
	   }
	printk("Xilinx Chip successfully loaded, configured and started!!\n");

	tor->mem8[SYNCREG] = 0;
	tor->mem8[CTLREG] = 0;
	tor->mem8[CTLREG1] = 0;
	tor->mem8[LEDREG] = 0;

	/* check part revision data */
	x = t1in(tor,1,0xf) & 15;
#ifdef	NONREVA
	if (x > 3)
	{
		tor->mem8[CTLREG1] = NONREVA;
	}
#endif
	for (x = 0; x < 256; x++) tor->mem32[x] = 0x7f7f7f7f;


	if (request_irq(tor->irq, tor2_intr, SA_INTERRUPT | SA_SHIRQ, "tor2", tor)) {
		printk(KERN_ERR "Unable to request tormenta IRQ %d\n", tor->irq);
		goto err_out_release_all;
	}

	if (t1in(tor,1,0xf) & 0x80) {
		printk("Tormenta 2 Quad E1/PRA Card\n");
		tor->cardtype = TYPE_E1;
		tor->datxlt = datxlt_e1;
	} else {
		printk("Tormenta 2 Quad T1/PRI Card\n");
		tor->cardtype = TYPE_T1;
		tor->datxlt = datxlt_t1;
	}
	init_spans(tor); 

	tor->order = tor->mem8[SWREG];
	printk("Detected Card number: %d\n", tor->order);

	/* Launch cards as appropriate */
	x = 0;
	for (;;) {
		/* Find a card to activate */
		f = 0;
		for (x=0;cards[x];x++) {
			if (cards[x]->order <= highestorder) {
				tor2_launch(cards[x]);
				if (cards[x]->order == highestorder)
					f = 1;
			}
		}
		/* If we found at least one, increment the highest order and search again, otherwise stop */
		if (f) 
			highestorder++;
		else
			break;
	}

	return 0;

err_out_release_all:
	release_mem_region(tor->xilinx32_region, tor->xilinx32_len);
	release_mem_region(tor->xilinx8_region, tor->xilinx8_len);
err_out_release_plx_region:
	release_mem_region(tor->plx_region, tor->plx_len);
err_out_free_tor:
	if (tor->plx) iounmap((void *)tor->plx);
	if (tor->mem8) iounmap((void *)tor->mem8);
	if (tor->mem32) iounmap((void *)tor->mem32);
	if (tor) {
		for (x = 0; x < 3; x++) kfree(tor->chans[x]);
		kfree(tor);
	}
	return -ENODEV;
}

static struct pci_driver tor2_driver;

static void __devexit tor2_remove(struct pci_dev *pdev)
{
	int x;
	struct tor2 *tor;
	tor = pci_get_drvdata(pdev);
	if (!tor)
		BUG();
	tor->mem8[SYNCREG] = 0;
	tor->mem8[CTLREG] = 0;
	tor->mem8[LEDREG] = 0;
	tor->plx[INTCSR] = cpu_to_le16(0);
	free_irq(tor->irq, tor);
	if (tor->spans[0].flags & ZT_FLAG_REGISTERED)
		zt_unregister(&tor->spans[0]);
	if (tor->spans[1].flags & ZT_FLAG_REGISTERED)
		zt_unregister(&tor->spans[1]);
	if (tor->spans[2].flags & ZT_FLAG_REGISTERED)
		zt_unregister(&tor->spans[2]);
	if (tor->spans[3].flags & ZT_FLAG_REGISTERED)
		zt_unregister(&tor->spans[3]);
	release_mem_region(tor->plx_region, tor->plx_len);
	release_mem_region(tor->xilinx32_region, tor->xilinx32_len);
	release_mem_region(tor->xilinx8_region, tor->xilinx8_len);
	if (tor->plx) iounmap((void *)tor->plx);
	if (tor->mem8) iounmap((void *)tor->mem8);
	if (tor->mem32) iounmap((void *)tor->mem32);

	cards[tor->num] = 0;
	pci_set_drvdata(pdev, NULL);
	for (x = 0; x < 3; x++) 
		if (tor->chans[x])
			kfree(tor->chans[x]);
	kfree(tor);
}

static struct pci_driver tor2_driver = {
	name: "tormenta2",
	probe: tor2_probe,
#ifdef LINUX26
	remove: __devexit_p(tor2_remove),
#else
	remove: tor2_remove,
#endif
	id_table: tor2_pci_ids,
};

static int __init tor2_init(void) {
	int res;
	res = pci_module_init(&tor2_driver);
	printk("Registered Tormenta2 PCI\n");
	return res;
}

static void __exit tor2_cleanup(void) {
	pci_unregister_driver(&tor2_driver);
	printk("Unregistered Tormenta2\n");
}

static void set_clear(struct tor2 *tor)
{
	int i,j,s;
	unsigned short val=0;
	for (s = 0; s < SPANS_PER_CARD; s++) {
		for (i = 0; i < 24; i++) {
			j = (i/8);
			if (tor->spans[s].chans[i].flags & ZT_FLAG_CLEAR) 
				val |= 1 << (i % 8);

			if ((i % 8)==7) {
#if 0
				printk("Putting %d in register %02x on span %d\n",
				       val, 0x39 + j, 1 + s);
#endif
				t1out(tor,1 + s, 0x39 + j, val);
				val = 0;
			}
		}
	}
		
}


static int tor2_rbsbits(struct zt_chan *chan, int bits)
{
	u_char m,c;
	int k,n,b;
	struct tor2_chan *p = chan->pvt;
	unsigned long flags;
#if 0
	printk("Setting bits to %d on channel %s\n", bits, chan->name);
#endif	
	if (p->tor->cardtype == TYPE_E1) { /* do it E1 way */
		if (chan->chanpos == 16) return 0;
		n = chan->chanpos - 1;
		if (chan->chanpos > 16) n--;
		k = p->span;
		b = (n % 15) + 1;
		c = p->tor->txsigs[k][b];
		m = (n / 15) * 4; /* nibble selector */
		c &= (15 << m); /* keep the other nibble */
		c |= (bits & 15) << (4 - m); /* put our new nibble here */
		p->tor->txsigs[k][b] = c;
		  /* output them to the chip */
		t1out(p->tor,k + 1,0x40 + b,c); 
		return 0;
	}						
	n = chan->chanpos - 1;
	k = p->span;
	b = (n / 8); /* get byte number */
	m = 1 << (n & 7); /* get mask */
	c = p->tor->txsigs[k][b];
	c &= ~m;  /* clear mask bit */
	  /* set mask bit, if bit is to be set */
	if (bits & ZT_ABIT) c |= m;
	p->tor->txsigs[k][b] = c;
	spin_lock_irqsave(&p->tor->lock, flags);	
	t1out(p->tor,k + 1,0x70 + b,c);
	b += 3; /* now points to b bit stuff */
	  /* get current signalling values */
	c = p->tor->txsigs[k][b];
	c &= ~m;  /* clear mask bit */
	  /* set mask bit, if bit is to be set */
	if (bits & ZT_BBIT) c |= m;
	  /* save new signalling values */
	p->tor->txsigs[k][b] = c;
	  /* output them into the chip */
	t1out(p->tor,k + 1,0x70 + b,c);
	b += 3; /* now points to c bit stuff */
	  /* get current signalling values */
	c = p->tor->txsigs[k][b];
	c &= ~m;  /* clear mask bit */
	  /* set mask bit, if bit is to be set */
	if (bits & ZT_CBIT) c |= m;
	  /* save new signalling values */
	p->tor->txsigs[k][b] = c;
	  /* output them into the chip */
	t1out(p->tor,k + 1,0x70 + b,c);
	b += 3; /* now points to d bit stuff */
	  /* get current signalling values */
	c = p->tor->txsigs[k][b];
	c &= ~m;  /* clear mask bit */
	  /* set mask bit, if bit is to be set */
	if (bits & ZT_DBIT) c |= m;
	  /* save new signalling values */
	p->tor->txsigs[k][b] = c;
	  /* output them into the chip */
	t1out(p->tor,k + 1,0x70 + b,c);
	spin_unlock_irqrestore(&p->tor->lock, flags);
	return 0;
}

static int tor2_shutdown(struct zt_span *span)
{
	int i;
	int tspan;
	int wasrunning;
	unsigned long flags;
	struct tor2_span *p = span->pvt;

	tspan = p->span + 1;
	if (tspan < 0) {
		printk("Tor2: Span '%d' isn't us?\n", span->spanno);
		return -1;
	}

	spin_lock_irqsave(&p->tor->lock, flags);
	wasrunning = span->flags & ZT_FLAG_RUNNING;

	span->flags &= ~ZT_FLAG_RUNNING;
	/* Zero out all registers */
	if (p->tor->cardtype == TYPE_E1) {
		for (i = 0; i < 192; i++)
			t1out(p->tor,tspan, i, 0);
	} else {
		for (i = 0; i < 160; i++)
			t1out(p->tor,tspan, i, 0);
	}
	if (wasrunning)
		p->tor->spansstarted--;
	spin_unlock_irqrestore(&p->tor->lock, flags);	
	if (!(p->tor->spans[0].flags & ZT_FLAG_RUNNING) &&
	    !(p->tor->spans[1].flags & ZT_FLAG_RUNNING) &&
	    !(p->tor->spans[2].flags & ZT_FLAG_RUNNING) &&
	    !(p->tor->spans[3].flags & ZT_FLAG_RUNNING))
		/* No longer in use, disable interrupts */
		p->tor->mem8[CTLREG] = 0;
	if (debug)
		printk("Span %d (%s) shutdown\n", span->spanno, span->name);
	return 0;
}


static int tor2_startup(struct zt_span *span)
{
	unsigned long endjif;
	int i;
	int tspan;
	unsigned long flags;
	char *coding;
	char *framing;
	char *crcing;
	int alreadyrunning;
	struct tor2_span *p = span->pvt;

	tspan = p->span + 1;
	if (tspan < 0) {
		printk("Tor2: Span '%d' isn't us?\n", span->spanno);
		return -1;
	}

	spin_lock_irqsave(&p->tor->lock, flags);

	alreadyrunning = span->flags & ZT_FLAG_RUNNING;

	/* initialize the start value for the entire chunk of last ec buffer */
	for (i = 0; i < span->channels; i++)
	{
		memset(p->tor->ec_chunk1[p->span][i],
			ZT_LIN2X(0,&span->chans[i]),ZT_CHUNKSIZE);
		memset(p->tor->ec_chunk2[p->span][i],
			ZT_LIN2X(0,&span->chans[i]),ZT_CHUNKSIZE);
	}
	/* Force re-evaluation of the timing source */
	if (timingcable)
		p->tor->syncsrc = -1;

	if (p->tor->cardtype == TYPE_E1) { /* if this is an E1 card */
		unsigned char tcr1,ccr1,tcr2;
		if (!alreadyrunning) {
			p->tor->mem8[SYNCREG] = SYNCSELF;
			p->tor->mem8[CTLREG] = E1DIV;
			p->tor->mem8[LEDREG] = 0;
			/* Force re-evaluation of sync src */
			/* Zero out all registers */
			for (i = 0; i < 192; i++) 
				t1out(p->tor,tspan, i, 0);
		
			/* Set up for Interleaved Serial Bus operation in byte mode */
			/* Set up all the spans every time, so we are sure they are
                           in a consistent state. If we don't, a card without all
                           its spans configured misbehaves in strange ways. */
			t1out(p->tor,1,0xb5,9); 
			t1out(p->tor,2,0xb5,8);
			t1out(p->tor,3,0xb5,8);
			t1out(p->tor,4,0xb5,8);

			t1out(p->tor,tspan,0x1a,4); /* CCR2: set LOTCMC */
			for (i = 0; i <= 8; i++) t1out(p->tor,tspan,i,0);
			for (i = 0x10; i <= 0x4f; i++) if (i != 0x1a) t1out(p->tor,tspan,i,0);
			t1out(p->tor,tspan,0x10,0x20); /* RCR1: Rsync as input */
			t1out(p->tor,tspan,0x11,6); /* RCR2: Sysclk=2.048 Mhz */
			t1out(p->tor,tspan,0x12,9); /* TCR1: TSiS mode */
		}
		ccr1 = 0;
		crcing = "";
		tcr1 = 9; /* base TCR1 value: TSis mode */
		tcr2 = 0;
		if (span->lineconfig & ZT_CONFIG_CCS) {
			ccr1 |= 8; /* CCR1: Rx Sig mode: CCS */
			coding = "CCS";
		} else {
			tcr1 |= 0x20; 
			coding = "CAS";
		}
		if (span->lineconfig & ZT_CONFIG_HDB3) {
			ccr1 |= 0x44; /* CCR1: TX and RX HDB3 */
			framing = "HDB3";
		} else framing = "AMI";
		if (span->lineconfig & ZT_CONFIG_CRC4) {
			ccr1 |= 0x11; /* CCR1: TX and TX CRC4 */
			tcr2 |= 0x02; /* TCR2: CRC4 bit auto */
			crcing = "/CRC4";
		} 
		t1out(p->tor,tspan,0x12,tcr1);
		t1out(p->tor,tspan,0x13,tcr2);
		t1out(p->tor,tspan,0x14,ccr1);
		t1out(p->tor,tspan, 0x18, 0x20); /* 120 Ohm, normal */

		if (!alreadyrunning) {
			t1out(p->tor,tspan,0x1b,0x8a); /* CCR3: LIRST & TSCLKM */
			t1out(p->tor,tspan,0x20,0x1b); /* TAFR */
			t1out(p->tor,tspan,0x21,0x5f); /* TNAFR */
			t1out(p->tor,tspan,0x40,0xb); /* TSR1 */
			for (i = 0x41; i <= 0x4f; i++) t1out(p->tor,tspan,i,0x55);
			for (i = 0x22; i <= 0x25; i++) t1out(p->tor,tspan,i,0xff);
			/* Wait 100 ms */
			endjif = jiffies + 10;
			spin_unlock_irqrestore(&p->tor->lock, flags);
			while (jiffies < endjif); /* wait 100 ms */
			spin_lock_irqsave(&p->tor->lock, flags);
			t1out(p->tor,tspan,0x1b,0x9a); /* CCR3: set also ESR */
			t1out(p->tor,tspan,0x1b,0x82); /* CCR3: TSCLKM only now */
			
			span->flags |= ZT_FLAG_RUNNING;
			p->tor->spansstarted++;

			/* enable interrupts */
			p->tor->mem8[CTLREG] = INTENA | E1DIV;
		}

		spin_unlock_irqrestore(&p->tor->lock, flags);

		if (debug) {
			if (alreadyrunning) 
				printk("Tor2: Reconfigured span %d (%s/%s%s) 120 Ohms\n", span->spanno, coding, framing, crcing);
			else
				printk("Tor2: Startup span %d (%s/%s%s) 120 Ohms\n", span->spanno, coding, framing, crcing);
		}
	} else { /* is a T1 card */

		if (!alreadyrunning) {
			p->tor->mem8[SYNCREG] = SYNCSELF;
			p->tor->mem8[CTLREG] = 0;
			p->tor->mem8[LEDREG] = 0;
			/* Zero out all registers */
			for (i = 0; i < 160; i++) 
				t1out(p->tor,tspan, i, 0);
		
			/* Set up for Interleaved Serial Bus operation in byte mode */
			/* Set up all the spans every time, so we are sure they are
                           in a consistent state. If we don't, a card without all
                           its spans configured misbehaves in strange ways. */
			t1out(p->tor,1,0x94,9); 
			t1out(p->tor,2,0x94,8);
			t1out(p->tor,3,0x94,8);
			t1out(p->tor,4,0x94,8);
			/* Full-on Sync required (RCR1) */
			t1out(p->tor,tspan, 0x2b, 8);	
			/* RSYNC is an input (RCR2) */
			t1out(p->tor,tspan, 0x2c, 8);	
			/* RBS enable (TCR1) */
			t1out(p->tor,tspan, 0x35, 0x10);
			/* TSYNC to be output (TCR2) */
			t1out(p->tor,tspan, 0x36, 4);
			/* Tx & Rx Elastic store, sysclk(s) = 2.048 mhz, loopback controls (CCR1) */
			t1out(p->tor,tspan, 0x37, 0x9c); 
			/* Set up received loopup and loopdown codes */
			t1out(p->tor,tspan, 0x12, 0x22); 
			t1out(p->tor,tspan, 0x14, 0x80); 
			t1out(p->tor,tspan, 0x15, 0x80); 
			/* Setup japanese mode if appropriate */
			t1out(p->tor,tspan,0x19,(japan ? 0x80 : 0x00)); /* no local loop */
			t1out(p->tor,tspan,0x1e,(japan ? 0x80 : 0x00)); /* no local loop */
		}
		/* Enable F bits pattern */
		i = 0x20;
		if (span->lineconfig & ZT_CONFIG_ESF)
			i = 0x88;
		if (span->lineconfig & ZT_CONFIG_B8ZS)
			i |= 0x44;
		t1out(p->tor,tspan, 0x38, i);
		if (i & 0x80)
			coding = "ESF";
		else
			coding = "SF";
		if (i & 0x40)
			framing = "B8ZS";
		else {
			framing = "AMI";
			t1out(p->tor,tspan,0x7e,0x1c); /* F bits pattern (0x1c) into FDL register */
		}
		t1out(p->tor,tspan, 0x7c, span->txlevel << 5);
	
		if (!alreadyrunning) {	
			/* LIRST to reset line interface */
			t1out(p->tor,tspan, 0x0a, 0x80);
	
			/* Wait 100 ms */
			endjif = jiffies + 10;

			spin_unlock_irqrestore(&p->tor->lock, flags);
	
			while (jiffies < endjif); /* wait 100 ms */

			spin_lock_irqsave(&p->tor->lock, flags);
	
			t1out(p->tor,tspan,0x0a,0x30); /* LIRST back to normal, Resetting elastic stores */

			span->flags |= ZT_FLAG_RUNNING;
			p->tor->spansstarted++;

			/* enable interrupts */
			p->tor->mem8[CTLREG] = INTENA;
		}

		set_clear(p->tor);

		spin_unlock_irqrestore(&p->tor->lock, flags);

		if (debug) {
			if (alreadyrunning) 
				printk("Tor2: Reconfigured span %d (%s/%s) LBO: %s\n", span->spanno, coding, framing, zt_lboname(span->txlevel));
			else
				printk("Tor2: Startup span %d (%s/%s) LBO: %s\n", span->spanno, coding, framing, zt_lboname(span->txlevel));
		}
	}
	if (p->tor->syncs[0] == span->spanno) printk("SPAN %d: Primary Sync Source\n",span->spanno);
	if (p->tor->syncs[1] == span->spanno) printk("SPAN %d: Secondary Sync Source\n",span->spanno);
	if (p->tor->syncs[2] == span->spanno) printk("SPAN %d: Tertiary Sync Source\n",span->spanno);
	if (p->tor->syncs[3] == span->spanno) printk("SPAN %d: Quaternary Sync Source\n",span->spanno);
	return 0;
}

static int tor2_maint(struct zt_span *span, int cmd)
{
	struct tor2_span *p = span->pvt;

	int tspan = p->span + 1;

	if (p->tor->cardtype == TYPE_E1)
	   {
		switch(cmd) {
		    case ZT_MAINT_NONE:
			t1out(p->tor,tspan,0xa8,0); /* no loops */
			break;
		    case ZT_MAINT_LOCALLOOP:
			t1out(p->tor,tspan,0xa8,0x40); /* local loop */
			break;
		    case ZT_MAINT_REMOTELOOP:
			t1out(p->tor,tspan,0xa8,0x80); /* remote loop */
			break;
		    case ZT_MAINT_LOOPUP:
		    case ZT_MAINT_LOOPDOWN:
		    case ZT_MAINT_LOOPSTOP: