at91sam7s256.h

专业汽车级嵌入式操作系统OSEK的源代码

  AT91_REG AIC_ISCR;		// Interrupt Set Command Register
  AT91_REG AIC_EOICR;		// End of Interrupt Command Register
  AT91_REG AIC_SPU;		// Spurious Vector Register
  AT91_REG AIC_DCR;		// Debug Control Register (Protect)
  AT91_REG Reserved1[1];	//
  AT91_REG AIC_FFER;		// Fast Forcing Enable Register
  AT91_REG AIC_FFDR;		// Fast Forcing Disable Register
  AT91_REG AIC_FFSR;		// Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;


// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#  define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0)	// (AIC) Priority Level
#  define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0)	// (AIC) Lowest priority level
#  define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7)	// (AIC) Highest priority level
#  define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5)	// (AIC) Interrupt Source Type
#  define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5)	// (AIC) Internal Sources Code Label Level Sensitive
#  define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5)	// (AIC) Internal Sources Code Label Edge triggered
#  define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5)	// (AIC) External Sources Code Label High-level Sensitive
#  define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5)	// (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#  define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0)	// (AIC) NFIQ Status
#  define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1)	// (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
#  define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0)	// (AIC) Protection Mode
#  define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1)	// (AIC) General Mask
  
// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
// *****************************************************************************
  typedef struct _AT91S_PDC {
  
AT91_REG PDC_RPR;		// Receive Pointer Register
  AT91_REG PDC_RCR;		// Receive Counter Register
  AT91_REG PDC_TPR;		// Transmit Pointer Register
  AT91_REG PDC_TCR;		// Transmit Counter Register
  AT91_REG PDC_RNPR;		// Receive Next Pointer Register
  AT91_REG PDC_RNCR;		// Receive Next Counter Register
  AT91_REG PDC_TNPR;		// Transmit Next Pointer Register
  AT91_REG PDC_TNCR;		// Transmit Next Counter Register
  AT91_REG PDC_PTCR;		// PDC Transfer Control Register
  AT91_REG PDC_PTSR;		// PDC Transfer Status Register
} AT91S_PDC, *AT91PS_PDC;


// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
#  define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0)	// (PDC) Receiver Transfer Enable
#  define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1)	// (PDC) Receiver Transfer Disable
#  define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8)	// (PDC) Transmitter Transfer Enable
#  define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9)	// (PDC) Transmitter Transfer Disable
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
  
// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Debug Unit
// *****************************************************************************
  typedef struct _AT91S_DBGU {
  
AT91_REG DBGU_CR;		// Control Register
  AT91_REG DBGU_MR;		// Mode Register
  AT91_REG DBGU_IER;		// Interrupt Enable Register
  AT91_REG DBGU_IDR;		// Interrupt Disable Register
  AT91_REG DBGU_IMR;		// Interrupt Mask Register
  AT91_REG DBGU_CSR;		// Channel Status Register
  AT91_REG DBGU_RHR;		// Receiver Holding Register
  AT91_REG DBGU_THR;		// Transmitter Holding Register
  AT91_REG DBGU_BRGR;		// Baud Rate Generator Register
  AT91_REG Reserved0[7];	//
  AT91_REG DBGU_CIDR;		// Chip ID Register
  AT91_REG DBGU_EXID;		// Chip ID Extension Register
  AT91_REG DBGU_FNTR;		// Force NTRST Register
  AT91_REG Reserved1[45];	//
  AT91_REG DBGU_RPR;		// Receive Pointer Register
  AT91_REG DBGU_RCR;		// Receive Counter Register
  AT91_REG DBGU_TPR;		// Transmit Pointer Register
  AT91_REG DBGU_TCR;		// Transmit Counter Register
  AT91_REG DBGU_RNPR;		// Receive Next Pointer Register
  AT91_REG DBGU_RNCR;		// Receive Next Counter Register
  AT91_REG DBGU_TNPR;		// Transmit Next Pointer Register
  AT91_REG DBGU_TNCR;		// Transmit Next Counter Register
  AT91_REG DBGU_PTCR;		// PDC Transfer Control Register
  AT91_REG DBGU_PTSR;		// PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;


// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
#  define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2)	// (DBGU) Reset Receiver
#  define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3)	// (DBGU) Reset Transmitter
#  define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4)	// (DBGU) Receiver Enable
#  define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5)	// (DBGU) Receiver Disable
#  define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6)	// (DBGU) Transmitter Enable
#  define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7)	// (DBGU) Transmitter Disable
#  define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8)	// (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#  define AT91C_US_PAR          ((unsigned int) 0x7 <<  9)	// (DBGU) Parity type
#  define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9)	// (DBGU) Even Parity
#  define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9)	// (DBGU) Odd Parity
#  define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9)	// (DBGU) Parity forced to 0 (Space)
#  define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9)	// (DBGU) Parity forced to 1 (Mark)
#  define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9)	// (DBGU) No Parity
#  define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9)	// (DBGU) Multi-drop mode
#  define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14)	// (DBGU) Channel Mode
#  define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14)	// (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#  define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14)	// (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#  define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14)	// (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#  define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14)	// (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#  define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0)	// (DBGU) RXRDY Interrupt
#  define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1)	// (DBGU) TXRDY Interrupt
#  define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3)	// (DBGU) End of Receive Transfer Interrupt
#  define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4)	// (DBGU) End of Transmit Interrupt
#  define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5)	// (DBGU) Overrun Interrupt
#  define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6)	// (DBGU) Framing Error Interrupt
#  define AT91C_US_PARE         ((unsigned int) 0x1 <<  7)	// (DBGU) Parity Error Interrupt
#  define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9)	// (DBGU) TXEMPTY Interrupt
#  define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11)	// (DBGU) TXBUFE Interrupt
#  define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12)	// (DBGU) RXBUFF Interrupt
#  define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30)	// (DBGU) COMM_TX Interrupt
#  define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31)	// (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#  define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0)	// (DBGU) Force NTRST in JTAG
  
// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
// *****************************************************************************
  typedef struct _AT91S_PIO {
  
AT91_REG PIO_PER;		// PIO Enable Register
  AT91_REG PIO_PDR;		// PIO Disable Register
  AT91_REG PIO_PSR;		// PIO Status Register
  AT91_REG Reserved0[1];	//
  AT91_REG PIO_OER;		// Output Enable Register
  AT91_REG PIO_ODR;		// Output Disable Registerr
  AT91_REG PIO_OSR;		// Output Status Register
  AT91_REG Reserved1[1];	//
  AT91_REG PIO_IFER;		// Input Filter Enable Register
  AT91_REG PIO_IFDR;		// Input Filter Disable Register
  AT91_REG PIO_IFSR;		// Input Filter Status Register
  AT91_REG Reserved2[1];	//
  AT91_REG PIO_SODR;		// Set Output Data Register
  AT91_REG PIO_CODR;		// Clear Output Data Register
  AT91_REG PIO_ODSR;		// Output Data Status Register
  AT91_REG PIO_PDSR;		// Pin Data Status Register
  AT91_REG PIO_IER;		// Interrupt Enable Register
  AT91_REG PIO_IDR;		// Interrupt Disable Register
  AT91_REG PIO_IMR;		// Interrupt Mask Register
  AT91_REG PIO_ISR;		// Interrupt Status Register
  AT91_REG PIO_MDER;		// Multi-driver Enable Register
  AT91_REG PIO_MDDR;		// Multi-driver Disable Register
  AT91_REG PIO_MDSR;		// Multi-driver Status Register
  AT91_REG Reserved3[1];	//
  AT91_REG PIO_PPUDR;		// Pull-up Disable Register
  AT91_REG PIO_PPUER;		// Pull-up Enable Register
  AT91_REG PIO_PPUSR;		// Pull-up Status Register
  AT91_REG Reserved4[1];	//
  AT91_REG PIO_ASR;		// Select A Register
  AT91_REG PIO_BSR;		// Select B Register
  AT91_REG PIO_ABSR;		// AB Select Status Register
  AT91_REG Reserved5[9];	//
  AT91_REG PIO_OWER;		// Output Write Enable Register
  AT91_REG PIO_OWDR;		// Output Write Disable Register
  AT91_REG PIO_OWSR;		// Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;


// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
// *****************************************************************************
  typedef struct _AT91S_CKGR {
  
AT91_REG CKGR_MOR;		// Main Oscillator Register
  AT91_REG CKGR_MCFR;		// Main Clock  Frequency Register
  AT91_REG Reserved0[1];	//
  AT91_REG CKGR_PLLR;		// PLL Register
} AT91S_CKGR, *AT91PS_CKGR;


// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#  define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0)	// (CKGR) Main Oscillator Enable
#  define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1)	// (CKGR) Main Oscillator Bypass
#  define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8)	// (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#  define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0)	// (CKGR) Main Clock Frequency
#  define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16)	// (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#  define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0)	// (CKGR) Divider Selected
#  define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0)	// (CKGR) Divider output is 0
#  define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1)	// (CKGR) Divider is bypassed
#  define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8)	// (CKGR) PLL Counter
#  define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14)	// (CKGR) PLL Output Frequency Range
#  define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14)	// (CKGR) Please refer to the PLL datasheet