at91sam7.h

专业汽车级嵌入式操作系统OSEK的源代码

#  define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0)	// (CKGR) Main Clock Frequency
#  define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16)	// (CKGR) Main Clock Ready
// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
#  define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0)	// (CKGR) Divider Selected
#  define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0)	// (CKGR) Divider output is 0
#  define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1)	// (CKGR) Divider is bypassed
#  define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8)	// (CKGR) PLL Counter
#  define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14)	// (CKGR) PLL Output Frequency Range
#  define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14)	// (CKGR) Please refer to the PLL datasheet
#  define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14)	// (CKGR) Please refer to the PLL datasheet
#  define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14)	// (CKGR) Please refer to the PLL datasheet
#  define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14)	// (CKGR) Please refer to the PLL datasheet
#  define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16)	// (CKGR) PLL Multiplier
#  define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28)	// (CKGR) Divider for USB Clocks
#  define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28)	// (CKGR) Divider output is PLL clock output
#  define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28)	// (CKGR) Divider output is PLL clock output divided by 2
#  define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28)	// (CKGR) Divider output is PLL clock output divided by 4

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Power Management Controler
// *****************************************************************************
typedef struct _AT91S_PMC {
  AT91_REG PMC_SCER;		// System Clock Enable Register
  AT91_REG PMC_SCDR;		// System Clock Disable Register
  AT91_REG PMC_SCSR;		// System Clock Status Register
  AT91_REG Reserved0[1];	// 
  AT91_REG PMC_PCER;		// Peripheral Clock Enable Register
  AT91_REG PMC_PCDR;		// Peripheral Clock Disable Register
  AT91_REG PMC_PCSR;		// Peripheral Clock Status Register
  AT91_REG Reserved1[1];	// 
  AT91_REG PMC_MOR;		// Main Oscillator Register
  AT91_REG PMC_MCFR;		// Main Clock  Frequency Register
  AT91_REG Reserved2[1];	// 
  AT91_REG PMC_PLLR;		// PLL Register
  AT91_REG PMC_MCKR;		// Master Clock Register
  AT91_REG Reserved3[3];	// 
  AT91_REG PMC_PCKR[8];		// Programmable Clock Register
  AT91_REG PMC_IER;		// Interrupt Enable Register
  AT91_REG PMC_IDR;		// Interrupt Disable Register
  AT91_REG PMC_SR;		// Status Register
  AT91_REG PMC_IMR;		// Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;

// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
#  define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0)	// (PMC) Processor Clock
#  define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7)	// (PMC) USB Device Port Clock
#  define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8)	// (PMC) Programmable Clock Output
#  define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9)	// (PMC) Programmable Clock Output
#  define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10)	// (PMC) Programmable Clock Output
#  define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11)	// (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
#  define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0)	// (PMC) Programmable Clock Selection
#  define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0)	// (PMC) Slow Clock is selected
#  define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1)	// (PMC) Main Clock is selected
#  define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3)	// (PMC) Clock from PLL is selected
#  define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2)	// (PMC) Programmable Clock Prescaler
#  define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2)	// (PMC) Selected clock
#  define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2)	// (PMC) Selected clock divided by 2
#  define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2)	// (PMC) Selected clock divided by 4
#  define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2)	// (PMC) Selected clock divided by 8
#  define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2)	// (PMC) Selected clock divided by 16
#  define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2)	// (PMC) Selected clock divided by 32
#  define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2)	// (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
#  define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0)	// (PMC) MOSC Status/Enable/Disable/Mask
#  define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2)	// (PMC) PLL Status/Enable/Disable/Mask
#  define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3)	// (PMC) MCK_RDY Status/Enable/Disable/Mask
#  define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8)	// (PMC) PCK0_RDY Status/Enable/Disable/Mask
#  define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9)	// (PMC) PCK1_RDY Status/Enable/Disable/Mask
#  define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10)	// (PMC) PCK2_RDY Status/Enable/Disable/Mask
#  define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11)	// (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
// *****************************************************************************
typedef struct _AT91S_RSTC {
  AT91_REG RSTC_RCR;		// Reset Control Register
  AT91_REG RSTC_RSR;		// Reset Status Register
  AT91_REG RSTC_RMR;		// Reset Mode Register
} AT91S_RSTC, *AT91PS_RSTC;

// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
#  define AT91C_SYSC_PROCRST    ((unsigned int) 0x1 <<  0)	// (RSTC) Processor Reset
#  define AT91C_SYSC_ICERST     ((unsigned int) 0x1 <<  1)	// (RSTC) ICE Interface Reset
#  define AT91C_SYSC_PERRST     ((unsigned int) 0x1 <<  2)	// (RSTC) Peripheral Reset
#  define AT91C_SYSC_EXTRST     ((unsigned int) 0x1 <<  3)	// (RSTC) External Reset
#  define AT91C_SYSC_KEY        ((unsigned int) 0xFF << 24)	// (RSTC) Password
// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
#  define AT91C_SYSC_URSTS      ((unsigned int) 0x1 <<  0)	// (RSTC) User Reset Status
#  define AT91C_SYSC_BODSTS     ((unsigned int) 0x1 <<  1)	// (RSTC) Brown-out Detection Status
#  define AT91C_SYSC_RSTTYP     ((unsigned int) 0x7 <<  8)	// (RSTC) Reset Type
#  define 	AT91C_SYSC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8)	// (RSTC) Power-up Reset. VDDCORE rising.
#  define 	AT91C_SYSC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8)	// (RSTC) Watchdog Reset. Watchdog overflow occured.
#  define 	AT91C_SYSC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8)	// (RSTC) Software Reset. Processor reset required by the software.
#  define 	AT91C_SYSC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8)	// (RSTC) User Reset. NRST pin detected low.
#  define 	AT91C_SYSC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8)	// (RSTC) Brown-out Reset.
#  define AT91C_SYSC_NRSTL      ((unsigned int) 0x1 << 16)	// (RSTC) NRST pin level
#  define AT91C_SYSC_SRCMP      ((unsigned int) 0x1 << 17)	// (RSTC) Software Reset Command in Progress.
// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
#  define AT91C_SYSC_URSTEN     ((unsigned int) 0x1 <<  0)	// (RSTC) User Reset Enable
#  define AT91C_SYSC_URSTIEN    ((unsigned int) 0x1 <<  4)	// (RSTC) User Reset Interrupt Enable
#  define AT91C_SYSC_ERSTL      ((unsigned int) 0xF <<  8)	// (RSTC) User Reset Enable
#  define AT91C_SYSC_BODIEN     ((unsigned int) 0x1 << 16)	// (RSTC) Brown-out Detection Interrupt Enable

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_RTTC {
  AT91_REG RTTC_RTMR;		// Real-time Mode Register
  AT91_REG RTTC_RTAR;		// Real-time Alarm Register
  AT91_REG RTTC_RTVR;		// Real-time Value Register
  AT91_REG RTTC_RTSR;		// Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;

// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
#  define AT91C_SYSC_RTPRES     ((unsigned int) 0xFFFF <<  0)	// (RTTC) Real-time Timer Prescaler Value
#  define AT91C_SYSC_ALMIEN     ((unsigned int) 0x1 << 16)	// (RTTC) Alarm Interrupt Enable
#  define AT91C_SYSC_RTTINCIEN  ((unsigned int) 0x1 << 17)	// (RTTC) Real Time Timer Increment Interrupt Enable
#  define AT91C_SYSC_RTTRST     ((unsigned int) 0x1 << 18)	// (RTTC) Real Time Timer Restart
// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
#  define AT91C_SYSC_ALMV       ((unsigned int) 0x0 <<  0)	// (RTTC) Alarm Value
// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
#  define AT91C_SYSC_CRTV       ((unsigned int) 0x0 <<  0)	// (RTTC) Current Real-time Value
// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
#  define AT91C_SYSC_ALMS       ((unsigned int) 0x1 <<  0)	// (RTTC) Real-time Alarm Status
#  define AT91C_SYSC_RTTINC     ((unsigned int) 0x1 <<  1)	// (RTTC) Real-time Timer Increment

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_PITC {
  AT91_REG PITC_PIMR;		// Period Interval Mode Register
  AT91_REG PITC_PISR;		// Period Interval Status Register
  AT91_REG PITC_PIVR;		// Period Interval Value Register
  AT91_REG PITC_PIIR;		// Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;

// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
#  define AT91C_SYSC_PIV        ((unsigned int) 0xFFFFF <<  0)	// (PITC) Periodic Interval Value
#  define AT91C_SYSC_PITEN      ((unsigned int) 0x1 << 24)	// (PITC) Periodic Interval Timer Enabled
#  define AT91C_SYSC_PITIEN     ((unsigned int) 0x1 << 25)	// (PITC) Periodic Interval Timer Interrupt Enable
// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
#  define AT91C_SYSC_PITS       ((unsigned int) 0x1 <<  0)	// (PITC) Periodic Interval Timer Status
// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
#  define AT91C_SYSC_CPIV       ((unsigned int) 0xFFFFF <<  0)	// (PITC) Current Periodic Interval Value
#  define AT91C_SYSC_PICNT      ((unsigned int) 0xFFF << 20)	// (PITC) Periodic Interval Counter
// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_WDTC {
  AT91_REG WDTC_WDCR;		// Watchdog Control Register
  AT91_REG WDTC_WDMR;		// Watchdog Mode Register
  AT91_REG WDTC_WDSR;		// Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;

// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
#  define AT91C_SYSC_WDRSTT     ((unsigned int) 0x1 <<  0)	// (WDTC) Watchdog Restart
// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
#  define AT91C_SYSC_WDV        ((unsigned int) 0xFFF <<  0)	// (WDTC) Watchdog Timer Restart
#  define AT91C_SYSC_WDFIEN     ((unsigned int) 0x1 << 12)	// (WDTC) Watchdog Fault Interrupt Enable
#  define AT91C_SYSC_WDRSTEN    ((unsigned int) 0x1 << 13)	// (WDTC) Watchdog Reset Enable
#  define AT91C_SYSC_WDRPROC    ((unsigned int) 0x1 << 14)	// (WDTC) Watchdog Timer Restart
#  define AT91C_SYSC_WDDIS      ((unsigned int) 0x1 << 15)	// (WDTC) Watchdog Disable
#  define AT91C_SYSC_WDD        ((unsigned int) 0xFFF << 16)	// (WDTC) Watchdog Delta Value
#  define AT91C_SYSC_WDDBGHLT   ((unsigned int) 0x1 << 28)	// (WDTC) Watchdog Debug Halt
#  define AT91C_SYSC_WDIDLEHLT  ((unsigned int) 0x1 << 29)	// (WDTC) Watchdog Idle Halt
// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
#  define AT91C_SYSC_WDUNF      ((unsigned int) 0x1 <<  0)	// (WDTC) Watchdog Underflow
#  define AT91C_SYSC_WDERR      ((unsigned int) 0x1 <<  1)	// (WDTC) Watchdog Error

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
  AT91_REG MC_RCR;		// MC Remap Control Register
  AT91_REG MC_ASR;		// MC Abort Status Register
  AT91_REG MC_AASR;		// MC Abort Address Status Register
  AT91_REG Reserved0[21];	//