使用Linux ARM GCC编译器来编译

/* 
 * vivi/s3c2410/nand_read.c: Simple NAND read functions for booting from NAND
 *
 * Copyright (C) 2002 MIZI Research, Inc.
 *
 * Author: Hwang, Chideok <[e-mail]>
 * Date  : $Date: 2004/02/04 06:22:24 $
 *
 * $Revision: 1.1.1.1 $
 * $Id: param.c,v 1.9 2002/07/11 06:17:20 nandy Exp 
 *
 * History
 *
 * 2002-05-xx: Hwang, Chideok <[e-mail]>
 *
 * 2002-05-xx: Chan Gyun Jeong <[e-mail]>
 *
 * 2002-08-10: Yong-iL Joh <[e-mail]>
 *
 */

#include <config.h>

#define __REGb(x)	(*(volatile unsigned char *)(x))
#define __REGi(x)	(*(volatile unsigned int *)(x))
#define NF_BASE		0x4e000000

#define NFCONF		__REGi(NF_BASE + 0x0)
#define NFCONT		__REGi(NF_BASE + 0x4)
#define NFCMD		__REGb(NF_BASE + 0x8)
#define NFADDR		__REGb(NF_BASE + 0xC)
#define NFDATA		__REGb(NF_BASE + 0x10)
#define NFSTAT		__REGb(NF_BASE + 0x20)

//#define GPDAT		__REGi(GPIO_CTL_BASE+oGPIO_F+oGPIO_DAT)

#define NAND_CHIP_ENABLE  (NFCONT &= ~(1<<1))
#define NAND_CHIP_DISABLE (NFCONT |=  (1<<1))
#define NAND_CLEAR_RB	  (NFSTAT |=  (1<<2))
#define NAND_DETECT_RB	  { while(! (NFSTAT&(1<<2)) );}

#define BUSY 4
inline void wait_idle(void) {
	while(!(NFSTAT & BUSY));
	NFSTAT |= BUSY;
}

#define NAND_CMD_READ0		0
#define NAND_CMD_READSTART	0x30
#define NAND_CMD_READOOB	0x50
#define NAND_CMD_READID   0x90

#define PAGESPERSBLOCK      (32)
#define BYTESPERSPAGE       (512)
#define NAND_BLOCK_SMASK		(512 - 1)
#define PAGESPERLBLOCK      (64)
#define NAND_BLOCK_LMASK		(2048 - 1)

void PrintChar(char msg);

static int maf_id,dev_id=0x76;
/* low level nand read function */
static int
nand_read_smallpage(unsigned char *buf, unsigned long start_addr, int size)
{
  int addr,i,j,page;
  
	if ((start_addr & NAND_BLOCK_SMASK)/* || (size & NAND_BLOCK_MASK)*/) {
		return -1;	/* invalid alignment */
	}

	NAND_CHIP_ENABLE;

	for(addr=start_addr; addr<(start_addr+size); addr+=PAGESPERSBLOCK*BYTESPERSPAGE) {
		
  		/* READOOB */
  		NAND_CLEAR_RB;
  		NFCMD = NAND_CMD_READOOB;
  		
  		/* Write Address */
      NFADDR = 5;
      NFADDR = (addr >> 9) & 0xff;
      NFADDR = (addr >> 17) & 0xff;
      NFADDR = (addr >> 25) & 0xff;
      
      NAND_DETECT_RB;
      for (i=0;i<1000;i++);
      
      if ((NFDATA&0xff) != 0xff)
        continue;
      

  		for (page=0;page<PAGESPERSBLOCK*BYTESPERSPAGE;page+=BYTESPERSPAGE) {
    		/* READ0 */
    		NAND_CLEAR_RB;	    
    		NFCMD = NAND_CMD_READ0;
    
    		/* Write Address */
        NFADDR = (addr+page) & 0xff;
        NFADDR = ((addr+page) >> 9) & 0xff;
        NFADDR = ((addr+page) >> 17) & 0xff;
        NFADDR = ((addr+page) >> 25) & 0xff;
        
    		NAND_DETECT_RB;
    		for (i=0;i<100;i++);
    
    		for(j=0; j<BYTESPERSPAGE; j++) {
    			*buf = (NFDATA & 0xff);
    			buf++;
    		}
  	  }
	}

	NAND_CHIP_DISABLE;
	for (i=0;i<100;i++);
	return 0;
}

static int
nand_read_largepage(unsigned char *buf, unsigned long start_addr, int size)
{
  int addr,i,j,page;
  
	if ((start_addr & NAND_BLOCK_LMASK)/* || (size & NAND_BLOCK_MASK)*/) {
		return -1;	/* invalid alignment */
	}

	NAND_CHIP_ENABLE;

	for(addr=start_addr; addr<(start_addr+size); addr+=PAGESPERLBLOCK*2048) {
      /* READOOB */
  		NAND_CLEAR_RB;
  		NFCMD = NAND_CMD_READ0;
  		
  		/* Write Address */
      NFADDR = 0;
      NFADDR = 8;
      NFADDR = (addr >> 11) & 0xff;
      NFADDR = (addr >> 19) & 0xff;
      NFADDR = (addr >> 27) & 0x3;
      
      NFCMD = NAND_CMD_READSTART;
      
      NAND_DETECT_RB;
      for (i=0;i<1000;i++);
      
      if ((NFDATA&0xff) != 0xff) {
        //PrintChar('E');
        continue;
      }
    
      for (page=0;page<PAGESPERLBLOCK;page++) {
        /* READ0 */
    		NAND_CLEAR_RB;	    
    		NFCMD = NAND_CMD_READ0;
    
    		/* Write Address */
        NFADDR = (addr+page*2048) & 0xff;
        NFADDR = ((addr+page*2048) >> 8) & 0x07;
        NFADDR = ((addr+page*2048) >> 11) & 0xff;
        NFADDR = ((addr+page*2048) >> 19) & 0xff;
        NFADDR = ((addr+page*2048) >> 27) & 0x3;
        
        NFCMD = NAND_CMD_READSTART;
        
    		NAND_DETECT_RB;
        
        //PrintChar('.');
    		for(j=0; j<2048; j++) {
    			*buf = (NFDATA & 0xff);
    			buf++;
    		}
    	}
	}
	NAND_CHIP_DISABLE;
	for (i=0;i<100;i++);
	//PrintChar('O');
	return 0;
}

int
nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
{
	//if (dev_id==0x76) {
	  //PrintChar('S');
	  //PrintChar(' ');
	  return nand_read_smallpage(buf, start_addr, size);
	//} 
	
	//PrintChar('L');
	//PrintChar(' ');
	//return nand_read_largepage(buf, start_addr, size);
}
#if 0
	for(i=start_addr; i < (start_addr + size);) {
		if (dev_id==0x76) {
  		/* READ0 */
  		NAND_CLEAR_RB;	    
  		NFCMD = NAND_CMD_READ0;
  
  		/* Write Address */
      NFADDR = i & 0xff;
      NFADDR = (i >> 9) & 0xff;
      NFADDR = (i >> 17) & 0xff;
      NFADDR = (i >> 25) & 0xff;
      
  		NAND_DETECT_RB;
  
  		for(j=0; j < 512; j++) {
  			*buf = (NFDATA & 0xff);
  			buf++;
  		}
  		i += 512;
		} else {
      /* READ0 */
  		NAND_CLEAR_RB;	    
  		NFCMD = NAND_CMD_READ0;
  
  		/* Write Address */
      NFADDR = i & 0xff;
      NFADDR = (i >> 8) & 0x07;
      NFADDR = (i >> 11) & 0xff;
      NFADDR = (i >> 19) & 0xff;
      NFADDR = (i >> 27) & 0x3;
      
      NFCMD = NAND_CMD_READSTART;
      
  		NAND_DETECT_RB;
  
  		for(j=0; j < 2048; j++) {
  			*buf = (NFDATA & 0xff);
  			buf++;
  		}
  		i += 2048;
    }
	}
	NAND_CHIP_DISABLE;
	return 0;
}
#endif