my_clk_divider.vhd

Allegro原理图和PCB

-- my_clk_divider.vhd

library ieee;
use ieee.std_logic_1164.all;

entity CLK_DIVIDER is

    port(CLK, ACLR : in std_logic; DIVIDED_CLK1, DIVIDED_CLK2: out std_logic);

end CLK_DIVIDER;

architecture DEF_ARCH of CLK_DIVIDER is 

  component clockdiv
    port(Aclr, CLK : in std_logic; Q : out std_logic);
  end component;

    signal net : std_logic_vector (23 downto 0);

begin 

net(0) <= CLK;
DIVIDED_CLK1 <= net(22);
DIVIDED_CLK2 <= net(23);

GEN_label:        -- Note that a label is required here
    for i in 1 to 23 generate
        clk_div : clockdiv port map(ACLR, net(i-1), net(i));
    end generate;

    

end DEF_ARCH;