88.c

坦尼保姆

    case 0xC1: spare(t);
    case 0xC2: if(traceflag) procdepth(-1); IMMED; POP(t);
		CSMEM(pcx,t); sp += eop; LOOP;
    case 0xC3: if(traceflag) procdepth(-1); POP(t); CSMEM(pcx,t);
                 LOOP;
    case 0xC4: wd(); *rapw= eop; eapc+=2; WFETCH; es=eop; LOOP;
    case 0xC5: wd(); *rapw= eop; eapc+=2; WFETCH; ds=eop; LOOP;
    case 0xC6: by(); BSTORE(*pcx++); LOOP;	/* subopcodes ignored */
    case 0xC7: wd(); MOV16; LOOP;	/* subopcodes ignored */

    case 0xC8:
    case 0xC9: spare(t);
    case 0xCA: if(traceflag) procdepth(-1); IMMED; POP(t); POP(t2);
		CS(t2); CSMEM(pcx,t); sp+=eop; LOOP;
    case 0xCB: if(traceflag) procdepth(-1); POP(t); POP(t2); CS(t2);
		CSMEM(pcx,t); LOOP;
    case 0xCC: if(traceflag) procdepth(1); panic("int 3 executed.");
		interrupt(3); LOOP;
    case 0xCD: if(traceflag) procdepth(1); IMMED8Z; interrupt(eop); LOOP;
    case 0xCE: if(traceflag) procdepth(1); CC; if (ovf) interrupt(4); CC; LOOP;
    case 0xCF: if(traceflag) procdepth(-1); POP(t); POP(t2); CS(t2); POP(eop);
		CSMEM(pcx,t); LOADFLAGS(eop); if (intf) checkint(); LOOP;

    case 0xD0: by(); CC;
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case B00: BITSEL(cf,7,t,6); BSTORE(eoplo+eoplo+cf);
			ovf=(cf+t)&1; LOOP;
	    case B01: BITSEL(cf,0,t,7); BSTORE(((eoplo>>1)&0177) | (cf<<7));
			ovf=(cf+t)&1; LOOP;
	    case B02: BITSEL(n,7,t,6); BSTORE(eoplo+eoplo+cf); cf=n;
			ovf=(n+t)&1;LOOP;
	    case B03: BITSEL(n,7,t,0); BSTORE(((eoplo>>1)&0177)|(cf<<7));
			ovf=(cf+n)&1; cf=t; LOOP;
	    case B04: BITSEL(cf,7,t,6); BSTORE(eoplo+eoplo); ovf=(cf+t)&1; LOOP;
	    case B05: BITSEL(cf,0,ovf,7); BSTORE(((eoplo>>1)&0177)); LOOP;
	    case B06: spare(t);
	    case B07: BITSEL(cf,0,t,7); BSTORE(((eoplo>>1)&0177) | (t<<7));
			ovf=0; LOOP;
	}

    case 0xD1: wd(); CC;
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case W00: BITSEL(cf,15,t,14); eop+=eop+cf;
			WSTORE(eop); ovf=(cf+t)&1; LOOP;
	    case W01: BITSEL(cf,0,t,15); eop=((eop>>1)&077777) | (cf<<15);
			WSTORE(eop); ovf=(cf+t)&1; LOOP;
	    case W02: BITSEL(n,15,t,14); eop+=eop+cf;cf=n;
			WSTORE(eop);ovf=(n+t)&1;LOOP;
	    case W03: BITSEL(n,15,t,0); eop=((eop>>1)&077777)|(cf<<15);
			WSTORE(eop); ovf=(cf+n)&1; cf=t; LOOP;
	    case W04: BITSEL(cf,15,t,14); eop+=eop;
			WSTORE(eop); ovf=(cf+t)&1; LOOP;
	    case W05: BITSEL(cf,0,ovf,15); eop=((eop>>1)&077777);
			WSTORE(eop); LOOP;
	    case W06: spare(t);
	    case W07: BITSEL(cf,0,t,15); eop=((eop>>1)&077777) | (t<<15);
			WSTORE(eop); ovf=0; LOOP;
	}

    case 0xD2: by(); CC;
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case B00: n=cl; while(n--){
		    BITSEL(cf,7,t,6); eop+=eop+cf;} BSTORE(eoplo); LOOP;
	    case B01: n=cl; while(n--) {BITSEL(cf,0,t,7); 
		    eoplo=((eoplo>>1)&0177) | (cf<<7);} BSTORE(eoplo); LOOP;
	    case B02: n=cl; while(n--) {BITSEL(t,7,mm,6);
		    eop+=eop+cf; cf=t;} BSTORE(eoplo); LOOP;
	    case B03: n=cl; while(n--) {BITSEL(mm,7,t,0);
		    eoplo=((eoplo>>1)&0177)|(cf<<7); cf=t;} BSTORE(eoplo); LOOP;
	    case B04: n=cl; while(n--){
		    BITSEL(cf,7,t,6); eop+=eop;} BSTORE(eoplo); LOOP;
	    case B05: n=cl;
		    while(n--) { BITSEL(cf,0,t,7); eoplo=((eoplo>>1)&0177); }
		    BSTORE(eoplo); LOOP;
	    case B06: spare(t);
	    case B07: n=cl;
		    while(n--) {BITSEL(cf,0,t,7);
				eoplo=((eoplo>>1)&0177) | (t<<7);}
		    BSTORE(eoplo); ovf=0; LOOP;
	}

    case 0xD3: wd(); CC;
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case W00: n=cl; while(n--) {
		    BITSEL(cf,15,t,14); eop+=eop+cf;} WSTORE(eop); LOOP;
	    case W01: n=cl; while(n--) {BITSEL(cf,0,t,15);
		    eop=((eop>>1)&077777) | (cf<<15);} WSTORE(eop); LOOP;
	    case W02: n=cl; while(n--) {BITSEL(t,15,mm,14);
		    eop+=eop+cf; cf=t;} WSTORE(eop); LOOP;
	    case W03: n=cl; while(n--) {BITSEL(mm,15,t,0); 
		    eop=((eop>>1)&077777) | (cf<<15); cf=t;} WSTORE(eop); LOOP;
	    case W04: n=cl; while(n--) {
		    BITSEL(cf,15,t,14); eop+=eop;} WSTORE(eop); LOOP;
	    case W05: n=cl;
		    while(n--) {BITSEL(cf,0,t,15); eop=((eop>>1)&077777);}
		    WSTORE(eop); LOOP;
	    case W06: spare(t);
	    case W07: n=cl;
		    while(n--) {BITSEL(cf,0,t,15);
				eop=((eop>>1)&077777) | (t<<15);}
		    WSTORE(eop); ovf=0; LOOP;
	}

    case 0xD4:
    case 0xD5: notim(t);
    case 0xD6: spare(t);
    case 0xD7: eoplo=al; eophi=0; eop+= bx; MEM(eapc,ds,eop);
		BFETCH; al=eoplo; LOOP;
    case 0xD8: notim(t);

    case 0xD9:
    case 0xDA:
    case 0xDB:
    case 0xDC:
    case 0xDD:
    case 0xDE:
    case 0xDF: spare(t);

    case 0xE0: IMMED8X; CC; if ( (cx -=1) != 0 && zerof == 0) pcx+=eop; LOOP;
    case 0xE1: IMMED8X; CC; if ( (cx -=1) != 0 && zerof > 0) pcx+=eop; LOOP;
    case 0xE2: IMMED8X; if ( (cx -=1) != 0) pcx+=eop; LOOP;
    case 0xE3: IMMED8X; if (cx == 0) pcx+=eop; LOOP;
    case 0xE4: IMMED8Z; inio(eop,1); LOOP;
    case 0xE5: IMMED8Z; inio(eop,2); LOOP;
    case 0xE6: IMMED8Z; roplo=al; rophi=0; outio(eop,rop,1); LOOP;
    case 0xE7: IMMED8Z; outio(eop,ax,2); LOOP;
    case 0xE8: if(traceflag) procdepth(1); IMMED; t=PC; PUSH(t);
		CSMEM(pcx,t+eop); LOOP;
    case 0xE9: IMMED; t=PC+eop; CSMEM(pcx,t); LOOP;	/*careful: wraparound */
    case 0xEA: IMMED; roplo= *pcx++; rophi= *pcx++; CS(rop); CSMEM(pcx,eop); LOOP;
    case 0xEB: IMMED8X; t=PC+eop; CSMEM(pcx,t); LOOP;	/* wraparound */
    case 0xEC: inio(dx,1); LOOP;
    case 0xED: inio(dx,2); LOOP;
    case 0xEE: eoplo=al; eophi=0;  outio(dx,eop,1); LOOP;
    case 0xEF: outio(dx,ax,2); LOOP;

    case 0xF0: breakpt(); t = dumpt; goto bloop; /* ew break point trap */
	 /* vidsim(); LOOP;	dirty trick to trap video ram access */
    case 0xF1: spare(t);
    case 0xF2: t = *pcx++ & mask;
	switch(t) {
	    case 0xA4:
	/*	if (timer > (unsigned) cx) {
		    /* No interrupt during this instruction * /
		    timer -= cx;
	*/	    STRING; t=1-dirf-dirf; n= cx;
		    while(cx) {BSTORE(*xapc); eapc+=t; xapc+=t; (cx)--;} 
		    si += n*t;  di += n*t;
	/*	} else {
		    /* Interrupt this instruction. * /
		    k = cx - (timer - 1);
		    cx = timer - 1;
		    STRING; t=1-dirf-dirf; n= cx;
		    while(cx) {BSTORE(*xapc); eapc+=t; xapc+=t; (cx)--;} 
		    si += n*t;  di += n*t;
		    cx = k;
		    pcx -= 2;
		    timer = 1;
	       }
	*/       LOOP;
	    case 0xA5:
	/*	if (timer > (unsigned) cx) {
		    timer -= cx;
	*/	    STRING; t=2*(1-dirf-dirf); n= cx;
		    while(cx) {XSTORE(xapc); eapc+=t; xapc+=t; (cx)--; }
		    si += n*t;  di += n*t;
	/*       } else {
		    k = cx - (timer - 1);
		    cx = timer - 1;
		    STRING; t=2*(1-dirf-dirf); n= cx;
		    while(cx) {XSTORE(xapc); eapc+=t; xapc+=t; (cx)--; }
		    si += n*t;  di += n*t;
		    cx = k;
		    pcx -= 2;
		    timer = 1;
	       }
	*/       LOOP;
	    case 0xA6:
	    case 0xA7:
	    case 0xAE: while(cx) {rep(t); CC; (cx)--; if (zerof != 0) LOOP;}
			LOOP;
	    case 0xAA:
	    case 0xAB:
	    case 0xAC:
	    case 0xAD: while(cx) {rep(t); (cx)--;} LOOP;
	    case 0xAF: while( (cx)-- ) {rep(t); CC; if (zerof != 0) LOOP;} LOOP;
	    default: panic("REP followed by nonstring operator.");
	}

    case 0xF3: t = *pcx++ & mask;
	switch(t) {
	    case 0xA4:
	/*	if (timer > (unsigned) cx) {
		    /* No interrupt during this instruction * /
		    timer -= cx;
	*/	    STRING; t=1-dirf-dirf; n= cx;
		    while(cx) {BSTORE(*xapc); eapc+=t; xapc+=t; (cx)--;} 
		    si += n*t;  di += n*t;
	/*	} else {
		    /* Interrupt this instruction. * /
		    k = cx - (timer - 1);
		    cx = timer - 1;
		    STRING; t=1-dirf-dirf; n= cx;
		    while(cx) {BSTORE(*xapc); eapc+=t; xapc+=t; (cx)--;} 
		    si += n*t;  di += n*t;
		    cx = k;
		    pcx -= 2;
		    timer = 1;
	       }
	*/       LOOP;
	    case 0xA5:
	/*	if (timer > (unsigned) cx) {
		    timer -= cx;
	*/	    STRING; t=2*(1-dirf-dirf); n= cx;
		    while(cx) {XSTORE(xapc); eapc+=t; xapc+=t; (cx)--; }
		    si += n*t;  di += n*t;
	/*       } else {
		    k = cx - (timer - 1);
		    cx = timer - 1;
		    STRING; t=2*(1-dirf-dirf); n= cx;
		    while(cx) {XSTORE(xapc); eapc+=t; xapc+=t; (cx)--; }
		    si += n*t;  di += n*t;
		    cx = k;
		    pcx -= 2;
		    timer = 1;
	       }
	*/       LOOP;
	    case 0xA6:
	    case 0xA7:
	    case 0xAE:
	    case 0xAF: while( (cx)-- ) {rep(t); CC; if (zerof == 0) LOOP;} LOOP;

	    case 0xAA:
	    case 0xAB:
	    case 0xAC:
	    case 0xAD: while( (cx)-- ) {rep(t);} LOOP;
	    default: panic("REP followed by nonstring operator.");
	}

    case 0xF4: printf("Halt instruction executed.  End of run.\n"); 
	    write(2,"Normal exit\n",12); stat(); exit(0);
    case 0xF5: CC; cf=cf^1; LOOP;
    case 0xF6: by();
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case B00: BRMCONST; c=eoplo&roplo; BSZONLY(c); LOOP;
	    case B01: spare(t);
	    case B02: BSTORE(~eoplo); LOOP;
	    case B03: c= 0-eoplo; BSTORE(c); BLAZYCC(0,eoplo,SUBB); LOOP;
	    case B04: u1=(unchr)al; u2=(unchr)eoplo; u=u1*u2;ax=u;
		    cf=(u<256 ? 0 : 1); ovf=cf; ccvalid=1; LOOP;
	    case B05: t=(short)al; n=(short)eoplo; ax=t*n;
		    /*cf=((al>=0&&ah==0)||(al<0&&ah==0xFF)?0:1);*/
		    cf=(((!(al&0X80))&&ah==0)||((al&0X80)&&ah==0xFF)?0:1);
			 ovf=cf; ccvalid=1;LOOP;
	    case B06: u1=(adr)ax; u2=(adr)eoplo; u=u1/u2; al=(char)u;
		    if(u>255)interrupt(0); else ah=(char)(u1%u2); LOOP;
	    case B07: t=ax; n=(short)eoplo; mm=t/n; al=(char)mm;
		    if(mm>127||mm<-128)interrupt(0); 
		    else ah=(char)(t-mm*n); LOOP;
	}

    case 0xF7: wd();
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case W00: RMCONST; SZONLY(eop&rop); LOOP;
	    case W01: spare(t);
	    case W02: WSTORE((~eop)); LOOP;
	    case W03: t= 0-eop; WSTORE(t); LAZYCC(0,eop,SUBW); LOOP;
	    case W04: l1=(adr)ax; l2=(adr)eop; l1=l1*l2; ax=(short)l1;
		    dx= (l1>>16)&0177777;
		    cf=(l1<65536 ? 0 : 1); ovf=cf; ccvalid=1; LOOP;
	    case W05: l1= ax; l2= eop; l1=l1*l2; ax=(short)l1;
		    dx= (l1>>16)&0177777;
		    cf=(l1<65536 ? 0 : 1); ovf=cf; ccvalid=1; LOOP;
	    case W06: if (dx<0)
			panic("simulator can't handle dividends >=2**31");
			/* {printf("simulator can't handle dividends >=2**31\n");
			    abort();}*/
		    l1=(adr)dx; l1=(l1<<16)+(adr)ax; l2=(adr)eop;
		    l=l1/l2; ax=(short)l;
		    if (l>65535||l<-65535)interrupt(0); else dx=l1%l2; LOOP;
	    case W07: l1=(adr)dx; l1=(l1<<16)+(adr)ax; l2=eop; l=l1/l2;
		    /*ax=(short)l;if (l>65535||l<-65535)interrupt(0);*/
		    ax=(short)l;if (l>32767||l<-32767)interrupt(0);
		    else dx=l1%l2; LOOP;
	}

    case 0xF8: CC; cf=0; LOOP;
    case 0xF9: CC; cf=1; LOOP;
    case 0xFA: intf=0; LOOP;
    case 0xFB: intf=1; checkint(); LOOP;
    case 0xFC: dirf=0; LOOP;
    case 0xFD: dirf=1; LOOP;
    case 0xFE: by();
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case B00: CC; c=eoplo; BSTORE(c+1); BLAZYCC(c,1,INCB); LOOP;
	    case B01: CC; c=eoplo; BSTORE(c-1); BLAZYCC(c,1,DECB); LOOP;
	    default: spare(t);
	}

    case 0xFF: wd();
	switch(ra) {		/* this opcode splits on reg field (in ra) */
	    case W00: CC; t=eop; WSTORE(t+1); LAZYCC(t,1,INCW); LOOP;
	    case W01: CC; t=eop; WSTORE(t-1); LAZYCC(t,1,DECW); LOOP;
	    case W02: if(traceflag) procdepth(2); t=PC; PUSH(t); CSMEM(pcx,eop);
			LOOP;
	    case W03: if(traceflag) procdepth(2); PUSH(cs); PUSH(PC); t=eop;
			eapc+=2; WFETCH; CS(eop); CSMEM(pcx,t);
			LOOP;
	    case W04: CSMEM(pcx,eop); LOOP;
	    case W05: notim(t);	/* can't figure out which comes first, cs or off */
	    case W06: PUSH(eop); LOOP;
	    case W07: spare(t);
	}

    default: panic("Error.  bad opcode %x \n", --*pcx);
    /*default: printf("Error.  bad opcode %x \n", --*pcx); dump(); abort();*/
    }
}

rep(op)
register int op;
{
/* The string instructions (MOVS, CMPS, STOS, LODS, and SCAS are done here. */
  char c;

  switch(op) {
    case 0xA4: STRING; BSTORE(*xapc); BSIDI; return;
    case 0xA5: STRING; BSTORE(*xapc++); eapc++; BSTORE(*xapc); WSIDI; return;
    case 0xA6: STRING; BFETCH; BSIDI; BLAZYCC(*xapc,eoplo,SUBB); return;
    case 0xA7: STRING; WFETCH; roplo= *xapc++; rophi= *xapc; WSIDI; 
    		LAZYCC(rop,eop,SUBW); return;
    case 0xAA: MEM(eapc,es,di); BSTORE(al); BDIRF(di); return;
    case 0xAB: MEM(eapc,es,di); WSTORE(ax); WDIRF(di); return; 
    case 0xAC: MEM(xapc,ds,si); al= *xapc; BDIRF(si); return;
    case 0xAD: MEM(xapc,ds,si); al= *xapc++; ah= *xapc; WDIRF(si); return; 
    case 0xAE: MEM(eapc,es,di); BFETCH; c=al-eoplo; BDIRF(di);
		BLAZYCC(al,eoplo,SUBB); return;
    case 0xAF: MEM(eapc,es,di); WFETCH; WDIRF(di); 
		LAZYCC(ax,eop,SUBW); return;
  }
}


vidsim (){}
dumpck (){}
checkint (){}
inio (){}
outio (){}