dk3200ee_0.plg

uPSD3200系列MCU的EEPROM的仿真实例

Current project is: 'dk3200ee'

AHDL2BLF  ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'

  Processing equations.............

  Module parsing complete. Building logic network...

  Creating Berkeley PLA file dk3200ee.tt1...

Module 'dk3200ee' processing complete.

Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds

BLIFOPT  Open-ABEL Optimizer 
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file dk3200ee.xrf... 
Writing Open-ABEL (PLA) file dk3200ee.tt2...

BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds

DIOFFT  Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: dk3200ee.tt2.
Output file: dk3200ee.tt3.


DIOFFT complete. - Time 0 seconds

AHDL2BLF  ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'

  Processing equations.............

  Module parsing complete. Building logic network...

  Creating Berkeley PLA file dk3200ee.tt1...

Module 'dk3200ee' processing complete.

Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds

AHDL2BLF  ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'

  Processing equations.............

  Module parsing complete. Building logic network...

  Creating Berkeley PLA file dk3200ee.tt1...

Module 'dk3200ee' processing complete.

Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds

BLIFOPT  Open-ABEL Optimizer 
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file dk3200ee.xrf... 
Writing Open-ABEL (PLA) file dk3200ee.tt2...

BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds

DIOFFT  Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: dk3200ee.tt2.
Output file: dk3200ee.tt3.


DIOFFT complete. - Time 0 seconds

PSD Fitter - Logic Synthesis and Device Fitting
PSDsoft Express 8.30 Copyright (C) 1993-2004 STMicroelectronics, Inc.  All Rights Reserved.
PROJECT    : dk3200ee                         DATE : 10/01/2004
DEVICE     : uPSD3234A                        TIME : 12:09:41
FIT OPTION : Keep Current
DESCRIPTION: Demo for uPSD3234A EEPROM emulation 

  >> PSD Fitter complete - Successful Fitting
  >> View fitter report for detail
PSD Address Translation - Merge MCU Firmware with PSD 
PSDsoft Express 8.30 Copyright (C) 1993-2004 STMicroelectronics, Inc.  All Rights Reserved.
PROJECT    : dk3200ee                                 DATE : 10/01/2004
DEVICE     : uPSD3234A                                TIME : 12:09:54
  >> 
  >> Warning ADR002: No data file has been specified for FS1.
  >> Warning ADR002: No data file has been specified for FS2.
  >> Warning ADR002: No data file has been specified for FS3.
  >> Warning ADR002: No data file has been specified for FS4.
  >> Warning ADR002: No data file has been specified for FS5.
  >> Warning ADR002: No data file has been specified for FS6.
  >> Warning ADR002: No data file has been specified for FS7.
  >> Warning ADR002: No data file has been specified for CSBOOT0.
  >> Warning ADR002: No data file has been specified for CSBOOT1.
  >> Warning ADR002: No data file has been specified for CSBOOT2.
  >> Warning ADR002: No data file has been specified for CSBOOT3.
  >> Address Translation complete.
  >> 
Project 'dk3200ee' is closed