crt0.ppc

The Lite Evaluation/Demonstration Kit is intended to illustrate use of the AN3042. The AN3042 is c

; Set the value of Option Register 7 (OR7) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR7 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR7(r4)
; Set the value of Base Register 7 (BR7) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR7 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR7(r4)
; Set the value of Port A Pin Assignment Register (PAPAR) to $0000.
; 	Field DD0 (bit 0) = 0
; 	Field DD1 (bit 1) = 0
; 	Field DD2 (bit 2) = 0
; 	Field DD3 (bit 3) = 0
; 	Field DD4 (bit 4) = 0
; 	Field DD5 (bit 5) = 0
; 	Field DD6 (bit 6) = 0
; 	Field DD7 (bit 7) = 0
; 	Field DD8 (bit 8) = 0
; 	Field DD9 (bit 9) = 0
; 	Field DD10 (bit 10) = 0
; 	Field DD11 (bit 11) = 0
; 	Field DD12 (bit 12) = 0
; 	Field DD13 (bit 13) = 0
; 	Field DD14 (bit 14) = 0
; 	Field DD15 (bit 15) = 0
;        li      r3,0x0000         ; PAPAR = 0x0000
;        sth     r3,PAPAR(r4)
; Set the value of Port A Open-Drain Register (PAODR) to $0000.
; 	Field Reserved (bits 0-8) = 0
; 	Field OD9 (bit 9) = 0
; 	Field OD10 (bit 10) = 0
; 	Field OD11 (bit 11) = 0
; 	Field OD12 (bit 12) = 0
; 	Field Reserved (bit 13) = 0
; 	Field OD14 (bit 14) = 0
; 	Field Reserved (bit 15) = 0
;        li      r3,0x0000         ; PAODR = 0x0000
;        sth     r3,PAODR(r4)
; Set the value of Port A Data Direction Register (PADIR) to $0000.
; 	Field DR0 (bit 0) = 0
; 	Field DR1 (bit 1) = 0
; 	Field DR2 (bit 2) = 0
; 	Field DR3 (bit 3) = 0
; 	Field DR4 (bit 4) = 0
; 	Field DR5 (bit 5) = 0
; 	Field DR6 (bit 6) = 0
; 	Field DR7 (bit 7) = 0
; 	Field DR8 (bit 8) = 0
; 	Field DR9 (bit 9) = 0
; 	Field DR10 (bit 10) = 0
; 	Field DR11 (bit 11) = 0
; 	Field DR12 (bit 12) = 0
; 	Field DR13 (bit 13) = 0
; 	Field DR14 (bit 14) = 0
; 	Field DR15 (bit 15) = 0
;        li      r3,0x0000         ; PADIR = 0x0000
;        sth     r3,PADIR(r4)
; Set the value of Port A Data Register (PADAT) to $0000.
; 	Field D0 (bit 0) = 0
; 	Field D1 (bit 1) = 0
; 	Field D2 (bit 2) = 0
; 	Field D3 (bit 3) = 0
; 	Field D4 (bit 4) = 0
; 	Field D5 (bit 5) = 0
; 	Field D6 (bit 6) = 0
; 	Field D7 (bit 7) = 0
; 	Field D8 (bit 8) = 0
; 	Field D9 (bit 9) = 0
; 	Field D10 (bit 10) = 0
; 	Field D11 (bit 11) = 0
; 	Field D12 (bit 12) = 0
; 	Field D13 (bit 13) = 0
; 	Field D14 (bit 14) = 0
; 	Field D15 (bit 15) = 0
;        li      r3,0x0000         ; PADAT = 0x0000
;        sth     r3,PADAT(r4)
; Set the value of Port B Pin Assignment Register (PBPAR) to $00000000.
; 	Field Reserved (bits 0-13) = 0
; 	Field DD14 (bit 14) = 0
; 	Field DD15 (bit 15) = 0
; 	Field DD16 (bit 16) = 0
; 	Field DD17 (bit 17) = 0
; 	Field DD18 (bit 18) = 0
; 	Field DD19 (bit 19) = 0
; 	Field DD20 (bit 20) = 0
; 	Field DD21 (bit 21) = 0
; 	Field DD22 (bit 22) = 0
; 	Field DD23 (bit 23) = 0
; 	Field DD24 (bit 24) = 0
; 	Field DD25 (bit 25) = 0
; 	Field DD26 (bit 26) = 0
; 	Field DD27 (bit 27) = 0
; 	Field DD28 (bit 28) = 0
; 	Field DD29 (bit 29) = 0
; 	Field DD30 (bit 30) = 0
; 	Field DD31 (bit 31) = 0
;        lis     r3,0x0000         ; PBPAR = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,PBPAR(r4)
; Set the value of Port B Open-Drain Register (PBODR) to $0000.
; 	Field OD16 (bit 0) = 0
; 	Field OD17 (bit 1) = 0
; 	Field OD18 (bit 2) = 0
; 	Field OD19 (bit 3) = 0
; 	Field OD20 (bit 4) = 0
; 	Field OD21 (bit 5) = 0
; 	Field OD22 (bit 6) = 0
; 	Field OD23 (bit 7) = 0
; 	Field OD24 (bit 8) = 0
; 	Field OD25 (bit 9) = 0
; 	Field OD26 (bit 10) = 0
; 	Field OD27 (bit 11) = 0
; 	Field OD28 (bit 12) = 0
; 	Field OD29 (bit 13) = 0
; 	Field OD30 (bit 14) = 0
; 	Field OD31 (bit 15) = 0
;        li      r3,0x0000         ; PBODR = 0x0000
;        sth     r3,PBODR(r4)
; Set the value of Port B Data Direction Register (PBDIR) to $00000000.
; 	Field Reserved (bits 0-13) = 0
; 	Field DR14 (bit 14) = 0
; 	Field DR15 (bit 15) = 0
; 	Field DR16 (bit 16) = 0
; 	Field DR17 (bit 17) = 0
; 	Field DR18 (bit 18) = 0
; 	Field DR19 (bit 19) = 0
; 	Field DR20 (bit 20) = 0
; 	Field DR21 (bit 21) = 0
; 	Field DR22 (bit 22) = 0
; 	Field DR23 (bit 23) = 0
; 	Field DR24 (bit 24) = 0
; 	Field DR25 (bit 25) = 0
; 	Field DR26 (bit 26) = 0
; 	Field DR27 (bit 27) = 0
; 	Field DR28 (bit 28) = 0
; 	Field DR29 (bit 29) = 0
; 	Field DR30 (bit 30) = 0
; 	Field DR31 (bit 31) = 0
;        lis     r3,0x0000         ; PBDIR = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,PBDIR(r4)
; Set the value of Port B Data Register (PBDAT) to $00000000.
; 	Field Reserved (bits 0-13) = 0
; 	Field D14 (bit 14) = 0
; 	Field D15 (bit 15) = 0
; 	Field D16 (bit 16) = 0
; 	Field D17 (bit 17) = 0
; 	Field D18 (bit 18) = 0
; 	Field D19 (bit 19) = 0
; 	Field D20 (bit 20) = 0
; 	Field D21 (bit 21) = 0
; 	Field D22 (bit 22) = 0
; 	Field D23 (bit 23) = 0
; 	Field D24 (bit 24) = 0
; 	Field D25 (bit 25) = 0
; 	Field D26 (bit 26) = 0
; 	Field D27 (bit 27) = 0
; 	Field D28 (bit 28) = 0
; 	Field D29 (bit 29) = 0
; 	Field D30 (bit 30) = 0
; 	Field D31 (bit 31) = 0
;        lis     r3,0x0000         ; PBDAT = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,PBDAT(r4)
; Set the value of Port C Data Direction Register (PCDIR) to $0000.
; 	Field Reserved (bits 0-3) = 0
; 	Field DR4 (bit 4) = 0
; 	Field DR5 (bit 5) = 0
; 	Field DR6 (bit 6) = 0
; 	Field DR7 (bit 7) = 0
; 	Field DR8 (bit 8) = 0
; 	Field DR9 (bit 9) = 0
; 	Field DR10 (bit 10) = 0
; 	Field DR11 (bit 11) = 0
; 	Field DR12 (bit 12) = 0
; 	Field DR13 (bit 13) = 0
; 	Field DR14 (bit 14) = 0
; 	Field DR15 (bit 15) = 0
;        li      r3,0x0000         ; PCDIR = 0x0000
;        sth     r3,PCDIR(r4)
; Set the value of Port C Pin Assignment Register (PCPAR) to $0000.
; 	Field Reserved (bits 0-3) = 0
; 	Field DD4 (bit 4) = 0
; 	Field DD5 (bit 5) = 0
; 	Field DD6 (bit 6) = 0
; 	Field DD7 (bit 7) = 0
; 	Field DD8 (bit 8) = 0
; 	Field DD9 (bit 9) = 0
; 	Field DD10 (bit 10) = 0
; 	Field DD11 (bit 11) = 0
; 	Field DD12 (bit 12) = 0
; 	Field DD13 (bit 13) = 0
; 	Field DD14 (bit 14) = 0
; 	Field DD15 (bit 15) = 0
;        li      r3,0x0000         ; PCPAR = 0x0000
;        sth     r3,PCPAR(r4)
; Set the value of Port C Special Options Register (PCSO) to $0000.
; 	Field Reserved (bits 0-3) = 0
; 	Field CD4 (bit 4) = 0
; 	Field CTS4 (bit 5) = 0
; 	Field CD3 (bit 6) = 0
; 	Field CTS3 (bit 7) = 0
; 	Field CD2 (bit 8) = 0
; 	Field CTS2 (bit 9) = 0
; 	Field CD1 (bit 10) = 0
; 	Field CTS1 (bit 11) = 0
; 	Field Reserved (bits 12-13) = 0
; 	Field DREQ1 (bit 14) = 0
; 	Field DREQ0 (bit 15) = 0
;        li      r3,0x0000         ; PCSO = 0x0000
;        sth     r3,PCSO(r4)
; Set the value of Port C Interrupt Control Register (PCINT) to $0000.
; 	Field Reserved (bits 0-3) = 0
; 	Field EDM4 (bit 4) = 0
; 	Field EDM5 (bit 5) = 0
; 	Field EDM6 (bit 6) = 0
; 	Field EDM7 (bit 7) = 0
; 	Field EDM8 (bit 8) = 0
; 	Field EDM9 (bit 9) = 0
; 	Field EDM10 (bit 10) = 0
; 	Field EDM11 (bit 11) = 0
; 	Field EDM12 (bit 12) = 0
; 	Field EDM13 (bit 13) = 0
; 	Field EDM14 (bit 14) = 0
; 	Field EDM15 (bit 15) = 0
;        li      r3,0x0000         ; PCINT = 0x0000
;        sth     r3,PCINT(r4)
; Set the value of Port C Data Register (PCDAT) to $0000.
; 	Field Reserved (bits 0-3) = 0
; 	Field D4 (bit 4) = 0
; 	Field D5 (bit 5) = 0
; 	Field D6 (bit 6) = 0
; 	Field D7 (bit 7) = 0
; 	Field D8 (bit 8) = 0
; 	Field D9 (bit 9) = 0
; 	Field D10 (bit 10) = 0
; 	Field D11 (bit 11) = 0
; 	Field D12 (bit 12) = 0
; 	Field D13 (bit 13) = 0
; 	Field D14 (bit 14) = 0
; 	Field D15 (bit 15) = 0
;        li      r3,0x0000         ; PCDAT = 0x0000
;        sth     r3,PCDAT(r4)
; Set the value of Port D Pin Assignment Register (PDPAR) to $0000.
; 	Field Reserved (bits 0-2) = 0
; 	Field DD3 (bit 3) = 0
; 	Field DD4 (bit 4) = 0
; 	Field DD5 (bit 5) = 0
; 	Field DD6 (bit 6) = 0
; 	Field DD7 (bit 7) = 0
; 	Field DD8 (bit 8) = 0
; 	Field DD9 (bit 9) = 0
; 	Field DD10 (bit 10) = 0
; 	Field DD11 (bit 11) = 0
; 	Field DD12 (bit 12) = 0
; 	Field DD13 (bit 13) = 0
; 	Field DD14 (bit 14) = 0
; 	Field DD15 (bit 15) = 0
;        li      r3,0x0000         ; PDPAR = 0x0000
;        sth     r3,PDPAR(r4)
; Set the value of Port D Data Direction Register (PDDIR) to $0000.
; 	Field OD8 (bit 0) = 0
; 	Field OD10 (bit 1) = 0
; 	Field Reserved (bit 2) = 0
; 	Field DR3 (bit 3) = 0
; 	Field DR4 (bit 4) = 0
; 	Field DR5 (bit 5) = 0
; 	Field DR6 (bit 6) = 0
; 	Field DR7 (bit 7) = 0
; 	Field DR8 (bit 8) = 0
; 	Field DR9 (bit 9) = 0
; 	Field DR10 (bit 10) = 0
; 	Field DR11 (bit 11) = 0
; 	Field DR12 (bit 12) = 0
; 	Field DR13 (bit 13) = 0
; 	Field DR14 (bit 14) = 0
; 	Field DR15 (bit 15) = 0
;        li      r3,0x0000         ; PDDIR = 0x0000
;        sth     r3,PDDIR(r4)
; Set the value of Port D Data Register (PDDAT) to $0000.
; 	Field Reserved (bits 0-2) = 0
; 	Field D3 (bit 3) = 0
; 	Field D4 (bit 4) = 0
; 	Field D5 (bit 5) = 0
; 	Field D6 (bit 6) = 0
; 	Field D7 (bit 7) = 0
; 	Field D8 (bit 8) = 0
; 	Field D9 (bit 9) = 0
; 	Field D10 (bit 10) = 0
; 	Field D11 (bit 11) = 0
; 	Field D12 (bit 12) = 0
; 	Field D13 (bit 13) = 0
; 	Field D14 (bit 14) = 0
; 	Field D15 (bit 15) = 0
;        li      r3,0x0000         ; PDDAT = 0x0000
;        sth     r3,PDDAT(r4)



		 .globl Lret
/* Green Hills stuff starts here */


	mr	r6, r5			# move r3, r4, r5 down one
	mr	r5, r4			# ''
	mr	r4, r3			# ''
	li	r3, SYSCALL_HELLO	# try a syscall
	crclr	2	
;	bl	__dotsyscall		# ''
Lret:
	lis	r12, %hiadj(Lret)	# 
	addi	r12, r12, %lo(Lret)	# ''

	mtlr	r12
;	mflr	r12			# (retain address of Lret)
;	beq	regs_okay		# success, debugger is present

	lis	sp, %hiadj(__ghsend_stack-8)	# else set SP
	addi	sp, sp, %lo(__ghsend_stack-8)	# ''
	lis	r13, %hiadj(__ghsbegin_sdabase)	# SDA base register
	addi	r13, r13, %lo(__ghsbegin_sdabase) # ''
regs_okay:
	lis	r2, %hiadj(__ghsbegin_sdata2+0x8000)	# SDA2 base register
	addi	r2, r2, %lo(__ghsbegin_sdata2+0x8000)	# ''
	lis	r11, %hiadj(Lret)	# adjust r2 for PIC mode
	addi	r11, r11, %lo(Lret)	# ''
	subfc	r11, r11, r12		# ''
	add	r2, r2, r11		# ''
	addi	r13, r13, 0x4000	# Adjust SDA base register
	addi	r13, r13, 0x4000	# ''
	lis	r10, %hiadj(regtab-4)	# Point before reg init table
	addi	r10, r10, %lo(regtab-4)	# ''
	add	r10, r10, r11		# '' (adjust for PIC)


	; debug - strobe out the IMMR so we can have a look at it
    mfspr   r15,IMMR
    li      r14,0         
    and     r15,r15,r14

    lis     r14,CS3_HI_BASE	  ; Point to the LED
    ori     r14,r14,0

	stw		r15,0(r14)
	; end debug


	lwzu	r14, 4(r10)		# initialize some regs
	lwzu	r15, 4(r10)		# (for -globalreg support)
	lwzu	r16, 4(r10)		# ''
	lwzu	r17, 4(r10)		# ''
	lwzu	r18, 4(r10)		# ''
	lwzu	r19, 4(r10)		# ''
	lwzu	r20, 4(r10)		# ''
	lwzu	r21, 4(r10)		# ''
	lwzu	r22, 4(r10)		# ''
	lwzu	r23, 4(r10)		# ''
	li	r10, 0			# terminate stack-trace chain
	stw	r10, 0(sp)		# ''
	lis	r3, %hiadj(baseptrs-Lret) # load address of baseptrs array
	addi	r3, r3, %lo(baseptrs-Lret) # ''
	add	r3, r3, r12		# ''
	b	__ghs_ind_crt0		# go to C language code
	.size	_start,$-_start

/* Table for initializing registers, for -globalreg support.
 * If no initialized global regs are used these values will be 0
 */
regtab:
	.weak	__ghs_init_r14, __ghs_init_r15
	.long	__ghs_init_r14, __ghs_init_r15
	.weak	__ghs_init_r16, __ghs_init_r17
	.long	__ghs_init_r16, __ghs_init_r17
	.weak	__ghs_init_r18, __ghs_init_r19
	.long	__ghs_init_r18, __ghs_init_r19
	.weak	__ghs_init_r20, __ghs_init_r21
	.long	__ghs_init_r20, __ghs_init_r21
	.weak	__ghs_init_r22, __ghs_init_r23
	.long	__ghs_init_r22, __ghs_init_r23

baseptrs:
	.long	__ghsbegin_picbase
	.long	__ghsbegin_robase
	.long	__ghsbegin_pidbase

/* this section directive is NEEDED.  It causes secinfo to be a 
 * readonly section which ind_crt0.c may require for proper operation */
	.section ".secinfo", "a"


#endif