crt0.ppc

The Lite Evaluation/Demonstration Kit is intended to illustrate use of the AN3042. The AN3042 is c

; 	Field DD5 (bit 5) = 0
; 	Field DD6 (bit 6) = 0
; 	Field DD7 (bit 7) = 0
; 	Field DD8 (bit 8) = 0
; 	Field DD9 (bit 9) = 0
; 	Field DD10 (bit 10) = 0
; 	Field DD11 (bit 11) = 0
; 	Field DD12 (bit 12) = 0
; 	Field DD13 (bit 13) = 0
; 	Field DD14 (bit 14) = 0
; 	Field DD15 (bit 15) = 0
        li      r3,0x0000         ; PDPAR = 0x0000
        sth     r3,PDPAR(r4)
; Set the value of Port D Data Direction Register (PDDIR) to $0000.
; 	Field OD8 (bit 0) = 0
; 	Field OD10 (bit 1) = 0
; 	Field Reserved (bit 2) = 0
; 	Field DR3 (bit 3) = 0
; 	Field DR4 (bit 4) = 0
; 	Field DR5 (bit 5) = 0
; 	Field DR6 (bit 6) = 0
; 	Field DR7 (bit 7) = 0
; 	Field DR8 (bit 8) = 0
; 	Field DR9 (bit 9) = 0
; 	Field DR10 (bit 10) = 0
; 	Field DR11 (bit 11) = 0
; 	Field DR12 (bit 12) = 0
; 	Field DR13 (bit 13) = 0
; 	Field DR14 (bit 14) = 0
; 	Field DR15 (bit 15) = 0

        li      r3,0x0000         ; PDDIR = 0x0000
        sth     r3,PDDIR(r4)
; Set the value of Port D Data Register (PDDAT) to $0000.
; 	Field Reserved (bits 0-2) = 0
; 	Field D3 (bit 3) = 0
; 	Field D4 (bit 4) = 0
; 	Field D5 (bit 5) = 0
; 	Field D6 (bit 6) = 0
; 	Field D7 (bit 7) = 0
; 	Field D8 (bit 8) = 0
; 	Field D9 (bit 9) = 0
; 	Field D10 (bit 10) = 0
; 	Field D11 (bit 11) = 0
; 	Field D12 (bit 12) = 0
; 	Field D13 (bit 13) = 0
; 	Field D14 (bit 14) = 0
; 	Field D15 (bit 15) = 0
        li      r3,0x0000         ; PDDAT = 0x0000
        sth     r3,PDDAT(r4)
*/

;************************************************
; Tim's Version starts here
;************************************************
;
;	 
; Set the value of Internal Memory Map Register (IMMR) to $FF000000.
; 	Field ISB (bits 0-15) = 65280
; 	Field PARTNUM (bits 16-23) = 0
; 	Field MASKNUM (bits 24-31) = 0
;        lis     r4,0xFF00         ; IMMR = 0xFF000000
;        ori     r4,r4,0x0000      ; NOTE: use r4
;        mtspr   IMMR,r4
; Set the value of System Clock and Reset Control Register (SCCR) to $00000000.
; 	Field Reserved (bit 0) = 0
; 	Field COM (bits 1-2) = 0
; 	Field Reserved (bits 3-5) = 0
; 	Field TBS (bit 6) = 0
; 	Field RTDIV (bit 7) = 0
; 	Field RTSEL (bit 8) = 0
; 	Field CRQEN (bit 9) = 0
; 	Field PRQEN (bit 10) = 0
; 	Field Reserved (bits 11-12) = 0
; 	Field EBDF (bits 13-14) = 0
; 	Field Reserved (bits 15-16) = 0
; 	Field DFSYNC (bits 17-18) = 0
; 	Field DFBRG (bits 19-20) = 0
; 	Field DFNL (bits 21-23) = 0
; 	Field DFNH (bits 24-26) = 0
; 	Field Reserved (bits 27-31) = 0
;        lis     r3,0x0000         ; SCCR = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,SCCR(r4)
; Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00004000.
; 	Field MF (bits 0-11) = 0
; 	Field Reserved (bits 12-15) = 0
; 	Field SPLSS (bit 16) = 0
; 	Field TEXPS (bit 17) = 1
; 	Field Reserved (bit 18) = 0
; 	Field TMIST (bit 19) = 0
; 	Field Reserved (bit 20) = 0
; 	Field CSRC (bit 21) = 0
; 	Field LPM (bits 22-23) = 0
; 	Field CSR (bit 24) = 0
; 	Field LOLRE (bit 25) = 0
; 	Field FIOPD (bit 26) = 0
; 	Field Reserved (bits 27-31) = 0
;        lis     r3,0x0000         ; PLPRCR = 0x00004000
;        ori     r3,r3,0x4000
;        stw     r3,PLPRCR(r4)
; Set the value of System Protection Control Register (SYPCR) to $FFFFFF07.
; 	Field SWTC (bits 0-15) = 65535
; 	Field BMT (bits 16-23) = 255
; 	Field BME (bit 24) = 0
; 	Field Reserved (bits 25-27) = 0
; 	Field SWF (bit 28) = 0
; 	Field SWE (bit 29) = 0   DISABLES the watch dog
; 	Field SWRI (bit 30) = 1
; 	Field SWP (bit 31) = 1
;        lis     r3,0xFFFF         ; SYPCR = 0xFFFFFF03
;        ori     r3,r3,0xFF03
;        stw     r3,SYPCR(r4)
; Set the value of Periodic Interrupt Timer Register (PITR) to $00000000.
; 	Field PIT (bits 0-15) = 0
; 	Field Reserved (bits 16-31) = 0
;        lis     r3,0x0000         ; PITR = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,PITR(r4)
; Clear the Software Watchdog Timer by writing the software service sequence to the SWSR.
; This may need to be done periodically if the boot process takes very long.
; Set the value of Software Service Register (SWSR) to $556C.
; 	Field SWSR (bits 0-15) = 21868
;        li      r3,0x556C         ; SWSR = 0x556C
;        sth     r3,SWSR(r4)
; Set the value of Software Service Register (SWSR) to $AA39.
; 	Field SWSR (bits 0-15) = 43577
;        li      r3,0xAA39         ; SWSR = 0xAA39
;        sth     r3,SWSR(r4)
; Set the value of Command Register (CPCR) to $8001.
; 	Field RST (bit 0) = 1
; 	Field Reserved (bits 1-3) = 0
; 	Field OPCODE (bits 4-7) = 0
; 	Field CHNUM (bits 8-11) = 0
; 	Field Reserved (bits 12-14) = 0
; 	Field FLG (bit 15) = 1
;        li      r3,0x8001         ; CPCR = 0x8001
;        sth     r3,CPCR(r4)
; Set the value of SIU Module Configuration Register (SIUMCR) to $80000000.
; 	Field EARB (bit 0) = 1
; 	Field EARP (bits 1-3) = 0
; 	Field Reserved (bits 4-7) = 0
; 	Field DSHW (bit 8) = 0
; 	Field DBGC (bits 9-10) = 0
; 	Field DBPC (bits 11-12) = 0
; 	Field Reserved (bit 13) = 0
; 	Field FRC (bit 14) = 0
; 	Field DLK (bit 15) = 0
; 	Field OPAR (bit 16) = 0
; 	Field PNCS (bit 17) = 0
; 	Field DPC (bit 18) = 0
; 	Field MPRE (bit 19) = 0
; 	Field MLRC (bits 20-21) = 0
; 	Field AEME (bit 22) = 0
; 	Field SEME (bit 23) = 0
; 	Field BSC (bit 24) = 0
; 	Field GB5E (bit 25) = 0
; 	Field B2DD (bit 26) = 0
; 	Field B3DD (bit 27) = 0
; 	Field Reserved (bits 28-31) = 0
;        lis     r3,0x8000         ; SIUMCR = 0x80000000
;        ori     r3,r3,0x0000
;        stw     r3,SIUMCR(r4)
; Set the value of Memory Periodic Timer Prescaler (MPTPR) to $0200.
; 	Field PTP (bits 0-7) = 2
; 	Field Reserved (bits 8-15) = 0
;        li      r3,0x0200         ; MPTPR = 0x0200
;        sth     r3,MPTPR(r4)
; Set the value of Machine A Mode Register (MAMR) to $00001000.
; 	Field PTA (bits 0-7) = 0
; 	Field PTAE (bit 8) = 0
; 	Field AMA (bits 9-11) = 0
; 	Field Reserved (bit 12) = 0
; 	Field DSA (bits 13-14) = 0
; 	Field Reserved (bit 15) = 0
; 	Field G0CLA (bits 16-18) = 0
; 	Field GPL_A4DIS (bit 19) = 1
; 	Field RLFA (bits 20-23) = 0
; 	Field WLFA (bits 24-27) = 0
; 	Field TLFA (bits 28-31) = 0
;        lis     r3,0x0000         ; MAMR = 0x00001000
;        ori     r3,r3,0x1000
;        stw     r3,MAMR(r4)
; Set the value of Machine B Mode Register (MBMR) to $00001000.
; 	Field PTB (bits 0-7) = 0
; 	Field PTBE (bit 8) = 0
; 	Field AMB (bits 9-11) = 0
; 	Field Reserved (bit 12) = 0
; 	Field DSB (bits 13-14) = 0
; 	Field Reserved (bit 15) = 0
; 	Field G0CLB (bits 16-18) = 0
; 	Field GPL_B4DIS (bit 19) = 1
; 	Field RLFB (bits 20-23) = 0
; 	Field WLFB (bits 24-27) = 0
; 	Field TLFB (bits 28-31) = 0
;        lis     r3,0x0000         ; MBMR = 0x00001000
;        ori     r3,r3,0x1000
;        stw     r3,MBMR(r4)
; Set the value of Timebase Status and Control Register (TBSCR) to $0000.
; 	Field TBIRQ (bits 0-7) = 0
; 	Field REFA (bit 8) = 0
; 	Field REFB (bit 9) = 0
; 	Field Reserved (bits 10-11) = 0
; 	Field REFAE (bit 12) = 0
; 	Field REFBE (bit 13) = 0
; 	Field TBF (bit 14) = 0
; 	Field TBE (bit 15) = 0
;        li      r3,0x0000         ; TBSCR = 0x0000
;        sth     r3,TBSCR(r4)
; Set the value of Real-Time Clock Status and Control Register (RTCSC) to $0000.
; 	Field RTCIRQ (bits 0-7) = 0
; 	Field SEC (bit 8) = 0
; 	Field ALR (bit 9) = 0
; 	Field Reserved (bit 10) = 0
; 	Field 38K (bit 11) = 0
; 	Field SIE (bit 12) = 0
; 	Field ALE (bit 13) = 0
; 	Field RTF (bit 14) = 0
; 	Field RTE (bit 15) = 0
;        li      r3,0x0000         ; RTCSC = 0x0000
;        sth     r3,RTCSC(r4)
; Set the value of Periodic Interrupt Status and Control Register (PISCR) to $0001.
; 	Field PIRQ (bits 0-7) = 0
; 	Field PS (bit 8) = 0
; 	Field Reserved (bits 9-12) = 0
; 	Field PIE (bit 13) = 0
; 	Field PITF (bit 14) = 0
; 	Field PTE (bit 15) = 1
;        li      r3,0x0001         ; PISCR = 0x0001
;        sth     r3,PISCR(r4)
; Set the value of Option Register 0 (OR0) to $00000EFC.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 1
; 	Field ACS (bits 21-22) = 3
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 15
; 	Field SETA (bit 28) = 1
; 	Field TRLX (bit 29) = 1
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR0 = 0x00000EFC
;        ori     r3,r3,0x0EFC
;        stw     r3,OR0(r4)
; Set the value of Base Register 0 (BR0) to $00000001.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 1
;        lis     r3,0x0000         ; BR0 = 0x00000001
;        ori     r3,r3,0x0001
;        stw     r3,BR0(r4)
; Set the value of Option Register 1 (OR1) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR1 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR1(r4)
; Set the value of Base Register 1 (BR1) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR1 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR1(r4)
; Set the value of Option Register 2 (OR2) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR2 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR2(r4)
; Set the value of Base Register 2 (BR2) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR2 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR2(r4)
; Set the value of Option Register 3 (OR3) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR3 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR3(r4)
; Set the value of Base Register 3 (BR3) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR3 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR3(r4)
; Set the value of Option Register 4 (OR4) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR4 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR4(r4)
; Set the value of Base Register 4 (BR4) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR4 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR4(r4)
; Set the value of Option Register 5 (OR5) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR5 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR5(r4)
; Set the value of Base Register 5 (BR5) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR5 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR5(r4)
; Set the value of Option Register 6 (OR6) to $00000000.
; 	Field AM (bits 0-16) = 0
; 	Field ATM (bits 17-19) = 0
; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22) = 0
; 	Field BI (bit 23) = 0
; 	Field SCY (bits 24-27) = 0
; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 0
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0
;        lis     r3,0x0000         ; OR6 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,OR6(r4)
; Set the value of Base Register 6 (BR6) to $00000000.
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 0
; 	Field V (bit 31) = 0
;        lis     r3,0x0000         ; BR6 = 0x00000000
;        ori     r3,r3,0x0000
;        stw     r3,BR6(r4)