crt0.ppc

The Lite Evaluation/Demonstration Kit is intended to illustrate use of the AN3042. The AN3042 is c

/*
 *  Language Independent PPC Startup Module
 *
 *  Copyright 1983-1996
 *  by Green Hills Software Inc.
 *
 *  This program is the property of Green Hills Software, Inc,
 *  its contents are proprietary information and no part of it
 *  is to be disclosed to anyone except employees of Green Hills
 *  Software, Inc., or as agreed in writing signed by the President
 *  of Green Hills Software, Inc.
 */

#include "indsyscl.h"



SCCR	.equ	0x0280
PLPRCR	.equ	0x0284
SYPCR	.equ	0x0004
PITR	.equ	0x0248
SWSR	.equ	0x000E
CPCR	.equ	0x09C0
SIUMCR	.equ	0x0000
MPTPR	.equ	0x017A
MAMR	.equ	0x0170
MBMR	.equ	0x0174
TBSCR	.equ	0x0200
RTCSC	.equ	0x0220
PISCR	.equ	0x0240
OR0	.equ	0x0104
BR0	.equ	0x0100
OR1	.equ	0x010C
BR1	.equ	0x0108
OR2	.equ	0x0114
BR2	.equ	0x0110
OR3	.equ	0x011C
BR3	.equ	0x0118
OR4	.equ	0x0124
BR4	.equ	0x0120
OR5	.equ	0x012C
BR5	.equ	0x0128
OR6	.equ	0x0134
BR6	.equ	0x0130
OR7	.equ	0x013C
BR7	.equ	0x0138
PAPAR	.equ	0x0952
PAODR	.equ	0x0954
PADIR	.equ	0x0950
PADAT	.equ	0x0956
PBPAR	.equ	0x0ABC
PBODR	.equ	0x0AC2
PBDIR	.equ	0x0AB8
PBDAT	.equ	0x0AC4
PCDIR	.equ	0x0960
PCPAR	.equ	0x0962
PCSO	.equ	0x0964
PCINT	.equ	0x0968
PCDAT	.equ	0x0966
PDPAR	.equ	0x0972
PDDIR	.equ	0x0970
PDDAT	.equ	0x0976
CacheDisableCmd    .equ   0x0400   ; Cache Disable command 

CS1_HI_BASE	.equ 	0x0010	 ; AN3042
CS2_HI_BASE	.equ 	0x0020	 ; SRAM
CS3_HI_BASE	.equ 	0x0030	 ; Hex Display
CS0_HI_BASE	.equ	0xFFF0	 ; FlexROM/Flash


	.file	"crt0.ppc"

#if defined(EMBEDDED)

	.weak	__ghsend_stack
	.weak	__ghsbegin_picbase
	.weak	__ghsbegin_robase
	.weak	__ghsbegin_pidbase
	.weak	__ghsbegin_sdabase

	.text

	.globl _start




;****************************************************
; Tim's stuff starts here
;****************************************************


_start:

        mfspr   r4,IMMR
        li      r3,0         
        and     r4,r4,r3


; Disable Data Cache before accessing any registers 

	mfspr      r3,568
	lis        r3,CacheDisableCmd    ; DCache Disable command
	mtspr      568,r3




; Set System Clock and Reset Control Register (SCCR) to $02800000.
; 	Field Reserved (bit 0) = 0
; 	Field COM (bits 1-2) = 0
; 	Field Reserved (bits 3-5) = 0
; 	Field TBS (bit 6) = 1
; 	Field RTDIV (bit 7) = 0
; 	Field RTSEL (bit 8) = 1
; 	Field CRQEN (bit 9) = 0
; 	Field PRQEN (bit 10) = 0
; 	Field Reserved (bits 11-12) = 0
; 	Field EBDF (bits 13-14) = 0
; 	Field Reserved (bits 15-16) = 0
; 	Field DFSYNC (bits 17-18) = 0
; 	Field DFBRG (bits 19-20) = 0
; 	Field DFNL (bits 21-23) = 0
; 	Field DFNH (bits 24-26) = 0
; 	Field Reserved (bits 27-31) = 0
        lis     r3,0x0280         ; SCCR = 0x02800000
        ori     r3,r3,0x0000
        stw     r3,SCCR(r4)

; Set PLL, Low Power and Reset Control Register (PLPRCR) to $00004000.
; 	Field MF (bits 0-11) = 0
; 	Field Reserved (bits 12-15) = 0
; 	Field SPLSS (bit 16) = 0
; 	Field TEXPS (bit 17) = 1
; 	Field Reserved (bit 18) = 0
; 	Field TMIST (bit 19) = 0
; 	Field Reserved (bit 20) = 0
; 	Field CSRC (bit 21) = 0
; 	Field LPM (bits 22-23) = 0
; 	Field CSR (bit 24) = 0
; 	Field LOLRE (bit 25) = 0
; 	Field FIOPD (bit 26) = 0
; 	Field Reserved (bits 27-31) = 0
        lis     r3,0x0000         ; PLPRCR = 0x00004000
        ori     r3,r3,0x4000
        stw     r3,PLPRCR(r4)

; Set System Protection Control Register (SYPCR) to $FFFFFF03.
; 	Field SWTC (bits 0-15) = 65535
; 	Field BMT (bits 16-23) = 255
; 	Field BME (bit 24) = 0
; 	Field Reserved (bits 25-27) = 0
; 	Field SWF (bit 28) = 0
; 	Field SWE (bit 29) = 0		  ;; Disable the Software Watchdog Timer
; 	Field SWRI (bit 30) = 1
; 	Field SWP (bit 31) = 1
        lis     r3,0xFFFF         ; SYPCR = 0xFFFFFF03
        ori     r3,r3,0xFF03
        stw     r3,SYPCR(r4)

;; Not needed???  We disable the PIT below (in PISCR). 
; Set the value of Periodic Interrupt Timer Register (PITR) to $00000000.
; 	Field PIT (bits 0-15) = 0
; 	Field Reserved (bits 16-31) = 0
        lis     r3,0x0000         ; PITR = 0x00000000
        ori     r3,r3,0x0000
        stw     r3,PITR(r4)


;;Not needed??? We disable SWT above in SYPCR.
;;  "If the SWT is not needed, the user
;;  must clear the software watchdog enable (SWE) bit in the system protection control register
;;  (SYPCR) to disable it."
; Clear the Software Watchdog Timer (SWT) by writing the software service sequence to the SWSR.
; This may need to be done periodically if the boot process takes very long.
; Set the value of Software Service Register (SWSR) to $556C.
; 	Field SWSR (bits 0-15) = 21868
        li      r3,0x556C         ; SWSR = 0x556C
        sth     r3,SWSR(r4)
; Set the value of Software Service Register (SWSR) to $AA39.
; 	Field SWSR (bits 0-15) = 43577
        li      r3,0xAA39         ; SWSR = 0xAA39	 1e0
        sth     r3,SWSR(r4)

;; Not needed???  Since we don't use the Communication Processor, why are we initializing???
; Set the value of Communication Processor Command Register (CPCR) to $8001.
; 	Field RST (bit 0) = 1
; 	Field Reserved (bits 1-3) = 0
; 	Field OPCODE (bits 4-7) = 0
; 	Field CHNUM (bits 8-11) = 0
; 	Field Reserved (bits 12-14) = 0
; 	Field FLG (bit 15) = 1
        li      r3,0x8001         ; CPCR = 0x8001
        sth     r3,CPCR(r4)

; Set the value of SIU Module Configuration Register (SIUMCR) to $00000000.
; 	Field EARB (bit 0) = 0
; 	Field EARP (bits 1-3) = 0
; 	Field Reserved (bits 4-7) = 0
; 	Field DSHW (bit 8) = 0
; 	Field DBGC (bits 9-10) = 0
; 	Field DBPC (bits 11-12) = 0
; 	Field Reserved (bit 13) = 0
; 	Field FRC (bit 14) = 0
; 	Field DLK (bit 15) = 0
; 	Field OPAR (bit 16) = 0
; 	Field PNCS (bit 17) = 0
; 	Field DPC (bit 18) = 0
; 	Field MPRE (bit 19) = 0
; 	Field MLRC (bits 20-21) = 0
; 	Field AEME (bit 22) = 0
; 	Field SEME (bit 23) = 0
; 	Field BSC (bit 24) = 0
; 	Field GB5E (bit 25) = 0
; 	Field B2DD (bit 26) = 0
; 	Field B3DD (bit 27) = 0
; 	Field Reserved (bits 28-31) = 0
        lis     r3,0x0000         ; SIUMCR = 0x00000000
        ori     r3,r3,0x0000
        stw     r3,SIUMCR(r4)


; Set the value of Memory Periodic Timer Prescaler (MPTPR) to $0200. (See p. 15-70 and Errata.)
; 	Field PTP (bits 0-7) = 2
; 	Field Reserved (bits 8-15) = 0
        li      r3,0x0200         ; MPTPR = 0x0200
        sth     r3,MPTPR(r4)

; Set the value of Machine A Mode Register (MAMR) to $00001000.
; 	Field PTA (bits 0-7) = 0
; 	Field PTAE (bit 8) = 0
; 	Field AMA (bits 9-11) = 0
; 	Field Reserved (bit 12) = 0
; 	Field DSA (bits 13-14) = 0
; 	Field Reserved (bit 15) = 0
; 	Field G0CLA (bits 16-18) = 0
; 	Field GPL_A4DIS (bit 19) = 1
; 	Field RLFA (bits 20-23) = 0
; 	Field WLFA (bits 24-27) = 0
; 	Field TLFA (bits 28-31) = 0
        lis     r3,0x0000         ; MAMR = 0x00001000
        ori     r3,r3,0x1000
        stw     r3,MAMR(r4)
; Set the value of Machine B Mode Register (MBMR) to $00001000.
; 	Field PTB (bits 0-7) = 0
; 	Field PTBE (bit 8) = 0
; 	Field AMB (bits 9-11) = 0
; 	Field Reserved (bit 12) = 0
; 	Field DSB (bits 13-14) = 0
; 	Field Reserved (bit 15) = 0
; 	Field G0CLB (bits 16-18) = 0
; 	Field GPL_B4DIS (bit 19) = 1
; 	Field RLFB (bits 20-23) = 0
; 	Field WLFB (bits 24-27) = 0
; 	Field TLFB (bits 28-31) = 0
        lis     r3,0x0000         ; MBMR = 0x00001000
        ori     r3,r3,0x1000
        stw     r3,MBMR(r4)

; Set the value of Timebase Status and Control Register (TBSCR) to $0000.
; 	Field TBIRQ (bits 0-7) = 0
; 	Field REFA (bit 8) = 0
; 	Field REFB (bit 9) = 0
; 	Field Reserved (bits 10-11) = 0
; 	Field REFAE (bit 12) = 0
; 	Field REFBE (bit 13) = 0
; 	Field TBF (bit 14) = 0
; 	Field TBE (bit 15) = 0
        li      r3,0x0000         ; TBSCR = 0x0000
        sth     r3,TBSCR(r4)
; Set the value of Real-Time Clock Status and Control Register (RTCSC) to $0000.
; 	Field RTCIRQ (bits 0-7) = 0
; 	Field SEC (bit 8) = 0
; 	Field ALR (bit 9) = 0
; 	Field Reserved (bit 10) = 0
; 	Field 38K (bit 11) = 0
; 	Field SIE (bit 12) = 0
; 	Field ALE (bit 13) = 0
; 	Field RTF (bit 14) = 0
; 	Field RTE (bit 15) = 0
;        li      r3,0x0000         ; RTCSC = 0x0000
;        sth     r3,RTCSC(r4)

; Set the value of Periodic Interrupt Status and Control Register (PISCR) to $0000.
; 	Field PIRQ (bits 0-7) = 0
; 	Field PS (bit 8) = 0
; 	Field Reserved (bits 9-12) = 0
; 	Field PIE (bit 13) = 0				; Disable the PIT Interrupt...
; 	Field PITF (bit 14) = 0
; 	Field PTE (bit 15) = 0				; ...and the Timer itself.
        li      r3,0x0000         ; PISCR = 0x0000
        sth     r3,PISCR(r4)



;;  'Boot Bank' OR0 (from MCUinit 6/19/98)
;;  Is intended to make *no* changes to OR0 and BR0 (virginal state), that is
;;   we write OR0 and BR0, but their contents are the same before and after the write.

;;  Has been modified from the above virginal state in several ways. See below.

; Set the value of Option Register 0 (OR0)

; 	Field AM (bits 0-16) = see above mods
; 	Field ATM (bits 17-19) = 000

; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22)  = 11
; 	Field BI (bit 23)       = 1

; 	Field SCY (bits 24-27) = 0100 = 4

; 	Field SETA (bit 28) = 0
; 	Field TRLX (bit 29) = 1
; 	Field EHTR (bit 30) = 0
; 	Field Reserved (bit 31) = 0

; The following is not the way we really want OR0.  We reload it the way we want it below, after
; initing the other OR/BR pairs.
        lis     r3,0x0000
        ori     r3,r3,0x0744
        stw     r3,OR0(r4)

; Set the value of Base Register 0 (BR0)
; 	Field BA (bits 0-16) = 131040
; 	Field AT (bits 17-19) = 000
; 	Field PS (bits 20-21) = 01
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 1

; 	Field MS (bits 24-25) = 00
; 	Field Reserved (bits 26-30) = 00 000
; 	Field V (bit 31) = 1
        lis     r3,0xFFF0
        ori     r3,r3,0x0501
        stw     r3,BR0(r4)



; Set the value of Option Register 1 (OR1)

; 	Field AM (bits 0-16) = 0xFFFF8

; 	Field ATM (bits 17-19) = 000

; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22)  = 00
; 	Field BI (bit 23)       = 1

; 	Field SCY (bits 24-27) = 1111 = 0xF     ; was 0100 = 4

; 	Field SETA (bit 28)     = 1		; Set SETA for boards that have RDYOUT# fix
; 	Field TRLX (bit 29)     = 0
; 	Field EHTR (bit 30)     = 0
; 	Field Reserved (bit 31) = 0
        lis     r3,0xFFFF 
        ori     r3,r3,0x81F8
        stw     r3,OR1(r4)

; Set the value of Base Register 1 (BR1)
; 	Field BA (bits 0-16) = 0
; 	Field AT (bits 17-19) = 0
; 	Field PS (bits 20-21) = 0
; 	Field PARE (bit 22) = 0
; 	Field WP (bit 23) = 0
; 	Field MS (bits 24-25) = 0
; 	Field Reserved (bits 26-30) = 00 000
; 	Field V (bit 31) = 1
        lis     r3,CS1_HI_BASE         
        ori     r3,r3,0x0001
        stw     r3,BR1(r4)



; Set the value of Option Register 2 (OR2)

; 	Field AM (bits 0-16) = 0xFFF00 (=32K)
; 	Field ATM (bits 17-19) = 000

; 	Field CSNT_SAM (bit 20) = 0
; 	Field ACS (bits 21-22)  = 11
; 	Field BI (bit 23)       = 1

; 	Field SCY (bits 24-27) = 0100 = 4

; 	Field SETA (bit 28)     = 0
; 	Field TRLX (bit 29)     = 1
; 	Field EHTR (bit 30)     = 0
; 	Field Reserved (bit 31) = 0
        lis     r3,0xFFF0 
        ori     r3,r3,0x0744
        stw     r3,OR2(r4)

; Set the value of Base Register 2 (BR2)
; 	Field BA (bits 0-16)  = 0
; 	Field AT (bits 17-19) = 000

; 	Field PS (bits 20-21) = 00
; 	Field PARE (bit 22)   = 0
; 	Field WP (bit 23)     = 0

; 	Field MS (bits 24-25)       = 00
; 	Field Reserved (bits 26-30) = 00 000
; 	Field V (bit 31) = 1
        lis     r3,CS2_HI_BASE         
        ori     r3,r3,0x0001
        stw     r3,BR2(r4)



; Set the value of Option Register 3 (OR3)