adsp-bf561ad.ldf.is

所用板ADSP-BF561 EZ-KIT Lite

	TYPE(RAM) WIDTH(8)
	START(0xFFA10000) END(0xFFA13FFF)
}
MEM_A_L1_CODE {		                            
	TYPE(RAM) WIDTH(8)
	START(0xFFA00000) END(0xFFA03FFF)
}
                       
                                                          
                   
                                  
 
                                                        
                   
                                  
 
                            
MEM_A_L1_DATA_B   {		                                   
	TYPE(RAM) WIDTH(8)
	START(0xFF901000) END(0xFF907FFF)
}
                          
MEM_A_L1_STACK    {		                                  
	TYPE(RAM) WIDTH(8)
	START(0xFF900000) END(0xFF900FFF)
}
                       
                                                          
                   
                                  
 
                                                 
                   
                                  
 
                            
MEM_A_L1_DATA_A   {		                            
	TYPE(RAM) WIDTH(8)
	START(0xFF800000) END(0xFF807FFF)
}
                          

                        
MEM_B_L1_SCRATCH {		                        
	TYPE(RAM) WIDTH(8)
	START(0xFF700000) END(0xFF700FFF)
}
MEM_B_L1_CODE_CACHE  {	                                     
	TYPE(RAM) WIDTH(8)
	START(0xFF610000) END(0xFF613FFF)
}
MEM_B_L1_CODE {		                               
	TYPE(RAM) WIDTH(8)
	START(0xFF600000) END(0xFF603FFF)
}
                       
                                                             
                   
                                  
 
                                                           
                   
                                  
 
                            
MEM_B_L1_DATA_B   {		                                      
	TYPE(RAM) WIDTH(8)
	START(0xFF501000) END(0xFF507FFF)
}
                          
MEM_B_L1_STACK    {		                                     
	TYPE(RAM) WIDTH(8)
	START(0xFF500000) END(0xFF500FFF)
}
                       
                                                             
                   
                                  
 
                                                    
                   
                                  
 
                            
MEM_B_L1_DATA_A   {		                               
	TYPE(RAM) WIDTH(8)
	START(0xFF400000) END(0xFF407FFF)
}
                          

                     
                                                 
                       
                       
                  
                                                                

                                        
                        
                             
                
                   
                                  
 
                         
                   
                   
                                  
 
                   
                   
                                  
 
                         
                   
                   
                                  
 
                        
     
                         
MEM_L2_HEAP_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB04000) END(0xFEB07FFF)
}
MEM_L2_SRAM_B     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB00000) END(0xFEB03FFF)
}
                         
                   
                   
                                  
 
                        
                        
                                        
                        
                  
                             
      
                
                   
                                  
 
                         
                   
                   
                                  
 
                   
                   
                                  
 
                         
                   
                   
                                  
 
                        
     
                 
MEM_L2_HEAP_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB0C000) END(0xFEB0FFFF)
}
MEM_L2_SRAM_A     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB08000) END(0xFEB0BFFF)
}
                         
                   
                   
                                  
 
                        
                        
               
MEM_L2_SRAM    { START(0xFEB10000) END(0xFEB1FFFF) TYPE(RAM) WIDTH(8) }
                                     
MEM_ASYNC3     { START(0x2C000000) END(0x2FFFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC2     { START(0x28000000) END(0x2BFFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC1     { START(0x24000000) END(0x27FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC0     { START(0x20000000) END(0x23FFFFFF) TYPE(RAM) WIDTH(8) }

                      
                                                                   
                                                   
                                                                  
                                                                
                                                                      
                                                                  
                                                                   
                                           
    

                
                                 
                                
                                    
                                                 
                                              
    
                                   
                              
      
              
MEM_SDRAM0_BANK0     { START(0x00000004) END(0x007FFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK1     { START(0x00800000) END(0x00FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK2     { START(0x01000000) END(0x017FFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK3     { START(0x01800000) END(0x01FFFFFF) TYPE(RAM) WIDTH(8) }
              
MEM_SDRAM1_BANK0     { START(0x02000000) END(0x027FFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM1_BANK1     { START(0x02800000) END(0x02FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM1_BANK2     { START(0x03000000) END(0x037FFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM1_BANK3     { START(0x03800000) END(0x03CFFFFF) TYPE(RAM) WIDTH(8) }
                   
MEM_SDRAM1_SHARED    { START(0x03D00000) END(0x03FFFFFF) TYPE(RAM) WIDTH(8) }
}

            
            
PROCESSOR p0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

                                                             
    RESOLVE(start,0xFFA00000)
                
                                      
      
    KEEP(start,_main)

    SECTIONS
    {
                                                            
                                                  
                                                                    
                                                             
                              
      
                                                                 
                                                                  
                                                               
      
    RESERVE(___waba0=0xFFB00FFF - 75,___la0=76)                   
                  
    RESERVE(___waba1=0xFFA13FFF - 75,___la1=76)                            
        
    RESERVE(___waba2=0xFFA03FFF - 75,___la2=76)                      
                 
                                                                   
       
    RESERVE(___waba4=0xFF907FFF - 75,___la4=76)                          
        
                 
                                                                   
       
    RESERVE(___waba6=0xFF807FFF - 75,___la6=76)                          
        
    RESERVE(___waba7=0xFEB1FFFF - 75,___la7=76)                
    RESERVE(___waba8=0x2FFFFFFF - 75,___la8=76)                     
                                    
    RESERVE(___waba9=0x3FFFFFF - 75,___la9=76)                           
                                                
                                                                   
        
      
                                                                              
                                               
                                                     

        l1_code {
            INPUT_SECTION_ALIGN(4)
            __CORE = 0;
            INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
        } >MEM_A_L1_CODE

        l1_code_cache {
                       
                                 
     
            ___l1_code_cache = 0;
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
                          
        } >MEM_A_L1_CODE_CACHE

                       
                         
                                  
                                   
                                
                          

        l1_data_a {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
                        
            ___l1_data_cache_a = 0;
                          
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS( $OBJECTS(data1) $LIBRARIES(data1))
                                                       
                                                             
                                                             
      
            INPUT_SECTIONS( $OBJECTS(constdata) $LIBRARIES(constdata))
        } >MEM_A_L1_DATA_A

        bsz_L1_data_a ZERO_INIT {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
        } >MEM_A_L1_DATA_A

                       
                         
                                  
                                   
                                
                          

        l1_data_b {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))
                        
            ___l1_data_cache_b = 0;