📄 p18f65j11.inc
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;----- ADCON1 Bits -----------------------------------------------------
PCFG0 EQU H'0000'
PCFG1 EQU H'0001'
PCFG2 EQU H'0002'
PCFG3 EQU H'0003'
VCFG0 EQU H'0004'
VCFG1 EQU H'0005'
;----- ADCON0 Bits -----------------------------------------------------
DONE EQU H'0001'
GO_DONE EQU H'0001'
ADON EQU H'0000'
GO EQU H'0001'
CHS0 EQU H'0002'
CHS1 EQU H'0003'
CHS2 EQU H'0004'
CHS3 EQU H'0005'
ADCAL EQU H'0007'
NOT_DONE EQU H'0001'
;----- SSP1CON2 Bits -----------------------------------------------------
SEN EQU H'0000'
RSEN EQU H'0001'
PEN EQU H'0002'
RCEN EQU H'0003'
ACKEN EQU H'0004'
ACKDT EQU H'0005'
ACKSTAT EQU H'0006'
GCEN EQU H'0007'
;----- SSPCON2 Bits -----------------------------------------------------
SEN EQU H'0000'
RSEN EQU H'0001'
PEN EQU H'0002'
RCEN EQU H'0003'
ACKEN EQU H'0004'
ACKDT EQU H'0005'
ACKSTAT EQU H'0006'
GCEN EQU H'0007'
;----- SSP1CON1 Bits -----------------------------------------------------
SSPM0 EQU H'0000'
SSPM1 EQU H'0001'
SSPM2 EQU H'0002'
SSPM3 EQU H'0003'
CKP EQU H'0004'
SSPEN EQU H'0005'
SSPOV EQU H'0006'
WCOL EQU H'0007'
;----- SSPCON1 Bits -----------------------------------------------------
SSPM0 EQU H'0000'
SSPM1 EQU H'0001'
SSPM2 EQU H'0002'
SSPM3 EQU H'0003'
CKP EQU H'0004'
SSPEN EQU H'0005'
SSPOV EQU H'0006'
WCOL EQU H'0007'
;----- SSP1STAT Bits -----------------------------------------------------
BF EQU H'0000'
UA EQU H'0001'
R_W EQU H'0002'
S EQU H'0003'
P EQU H'0004'
D_A EQU H'0005'
CKE EQU H'0006'
SMP EQU H'0007'
I2C_READ EQU H'0002'
I2C_START EQU H'0003'
I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- SSPSTAT Bits -----------------------------------------------------
BF EQU H'0000'
UA EQU H'0001'
R_W EQU H'0002'
S EQU H'0003'
P EQU H'0004'
D_A EQU H'0005'
CKE EQU H'0006'
SMP EQU H'0007'
I2C_READ EQU H'0002'
I2C_START EQU H'0003'
I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- T2CON Bits -----------------------------------------------------
T2CKPS0 EQU H'0000'
T2CKPS1 EQU H'0001'
TMR2ON EQU H'0002'
T2OUTPS0 EQU H'0003'
T2OUTPS1 EQU H'0004'
T2OUTPS2 EQU H'0005'
T2OUTPS3 EQU H'0006'
;----- T1CON Bits -----------------------------------------------------
TMR1ON EQU H'0000'
TMR1CS EQU H'0001'
T1SYNC EQU H'0002'
T1OSCEN EQU H'0003'
T1CKPS0 EQU H'0004'
T1CKPS1 EQU H'0005'
T1RUN EQU H'0006'
RD16 EQU H'0007'
T1INSYNC EQU H'0002'
NOT_T1SYNC EQU H'0002'
;----- RCON Bits -----------------------------------------------------
NOT_BOR EQU H'0000'
NOT_POR EQU H'0001'
NOT_PD EQU H'0002'
NOT_TO EQU H'0003'
NOT_RI EQU H'0004'
IPEN EQU H'0007'
BOR EQU H'0000'
POR EQU H'0001'
PD EQU H'0002'
TO EQU H'0003'
RI EQU H'0004'
;----- WDTCON Bits -----------------------------------------------------
SWDTEN EQU H'0000'
REGSLP EQU H'0007'
SWDTE EQU H'0000'
;----- OSCCON Bits -----------------------------------------------------
SCS0 EQU H'0000'
SCS1 EQU H'0001'
IOFS EQU H'0002'
OSTS EQU H'0003'
IRCF0 EQU H'0004'
IRCF1 EQU H'0005'
IRCF2 EQU H'0006'
IDLEN EQU H'0007'
;----- T0CON Bits -----------------------------------------------------
T0PS0 EQU H'0000'
T0PS1 EQU H'0001'
T0PS2 EQU H'0002'
PSA EQU H'0003'
T0SE EQU H'0004'
T0CS EQU H'0005'
T08BIT EQU H'0006'
TMR0ON EQU H'0007'
T0PS3 EQU H'0003'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1F EQU H'0000'
INT2F EQU H'0001'
INT3F EQU H'0002'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT3E EQU H'0005'
INT1P EQU H'0006'
INT2P EQU H'0007'
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT3IF EQU H'0002'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT3IE EQU H'0005'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
INT3P EQU H'0001'
T0IP EQU H'0002'
INTEDG3 EQU H'0003'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
INT3IP EQU H'0001'
TMR0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0F EQU H'0001'
T0IF EQU H'0002'
RBIE EQU H'0003'
INT0E EQU H'0004'
T0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKOVF EQU H'0007'
SP0 EQU H'0000'
SP1 EQU H'0001'
SP2 EQU H'0002'
SP3 EQU H'0003'
SP4 EQU H'0004'
STKFUL EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0800'-H'0F5F'
__BADRAM H'0F6B'-H'0F7D'
__BADRAM H'0F87'-H'0F88'
__BADRAM H'0F90'-H'0F91'
__BADRAM H'0F99'-H'0F9A'
__BADRAM H'0F9C'
__BADRAM H'0FA8'-H'0FAA'
__BADRAM H'0FB6'-H'0FBF'
__BADRAM H'0FD2'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Stack Overflow/Underflow Reset Enable bit:
; STVREN = OFF Reset on stack overflow/underflow disabled
; STVREN = ON Reset on stack overflow/underflow enabled
;
; Watchdog Timer Enable bit:
; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
; WDTEN = ON WDT enabled
;
; Code Protection bit:
; CP0 = ON Program memory is code-protected
; CP0 = OFF Program memory is not code-protected
;
; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
; IESO = OFF Two-Speed Start-up disabled
; IESO = ON Two-Speed Start-up enabled
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Default/Reset System Clock Select bit:
; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00
; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
;
; Oscillator Selection bits:
; FOSC = HS HS oscillator
; FOSC = HSPLL HS oscillator, PLL enabled and under software control
; FOSC = EC EC oscillator, CLKO function on OSC2
; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2
;
; Watchdog Timer Postscaler Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; ECCP2 MUX bit:
; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode
; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1L 7FF8h
; CONFIG1H 7FF9h
; CONFIG2L 7FFAh
; CONFIG2H 7FFBh
; CONFIG3L 7FFCh
; CONFIG3H 7FFDh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1L EQU H'7FF8'
_CONFIG1H EQU H'7FF9'
_CONFIG2L EQU H'7FFA'
_CONFIG2H EQU H'7FFB'
_CONFIG3L EQU H'7FFC'
_CONFIG3H EQU H'7FFD'
;----- CONFIG1L Options --------------------------------------------------
_DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
_DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
_XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
_STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled
_STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled
_WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit)
_WDTEN_ON_1L EQU H'FF' ; WDT enabled
;----- CONFIG1H Options --------------------------------------------------
_CP0_ON_1H EQU H'FB' ; Program memory is code-protected
_CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected
;----- CONFIG2L Options --------------------------------------------------
_IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled
_IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled
_FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled
_FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00
_FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
_FOSC_HS_2L EQU H'FC' ; HS oscillator
_FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control
_FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2
_FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2
;----- CONFIG2H Options --------------------------------------------------
_WDTPS_1_2H EQU H'F0' ; 1:1
_WDTPS_2_2H EQU H'F1' ; 1:2
_WDTPS_4_2H EQU H'F2' ; 1:4
_WDTPS_8_2H EQU H'F3' ; 1:8
_WDTPS_16_2H EQU H'F4' ; 1:16
_WDTPS_32_2H EQU H'F5' ; 1:32
_WDTPS_64_2H EQU H'F6' ; 1:64
_WDTPS_128_2H EQU H'F7' ; 1:128
_WDTPS_256_2H EQU H'F8' ; 1:256
_WDTPS_512_2H EQU H'F9' ; 1:512
_WDTPS_1024_2H EQU H'FA' ; 1:1024
_WDTPS_2048_2H EQU H'FB' ; 1:2048
_WDTPS_4096_2H EQU H'FC' ; 1:4096
_WDTPS_8192_2H EQU H'FD' ; 1:8192
_WDTPS_16384_2H EQU H'FE' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3L Options --------------------------------------------------
;----- CONFIG3H Options --------------------------------------------------
_CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode
_CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
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