if_athvar.h

Linux下wifi实现

	STAILQ_ENTRY(ath_buf) bf_list;
#ifdef ATH_SUPERG_FF
	TAILQ_ENTRY(ath_buf) bf_stagelist;	/* fast-frame staging list */
#endif
	struct ath_desc	*bf_desc;		/* virtual addr of desc */
	dma_addr_t bf_daddr;			/* physical addr of desc */
	struct sk_buff *bf_skb;			/* skbuff for buf */
	dma_addr_t bf_skbaddr;			/* physical addr of skb data */
	struct ieee80211_node *bf_node;		/* pointer to the node */
	u_int32_t bf_status;			/* status flags */
#ifdef ATH_SUPERG_FF
	/* XXX: combine this with bf_skbaddr if it ever changes to accomodate
	 *      multiple segments.
	 */
	u_int32_t bf_queueage; 			/* "age" of txq when this buffer placed on stageq */
	u_int16_t bf_numdesc;			/* number of descs used */
	u_int16_t bf_flags;			/* tx descriptor flags */
	dma_addr_t bf_skbaddrff[ATH_TXDESC-1]; 	/* extra addrs for ff */
#endif
};

/*
 * reset the rx buffer.
 * any new fields added to the athbuf and require 
 * reset need to be added to this macro.
 * currently bf_status is the only one requires that
 * requires reset.
 */
#define ATH_RXBUF_RESET(bf)	bf->bf_status=0

/* XXX: only managed for rx at the moment */
#define ATH_BUFSTATUS_DONE	0x00000001	/* hw processing complete, desc processed by hal */

/*
 * DMA state for tx/rx descriptors.
 */
struct ath_descdma {
	const char *dd_name;
	struct ath_desc	*dd_desc;	/* descriptors */
	dma_addr_t dd_desc_paddr;	/* physical addr of dd_desc */
	size_t dd_desc_len;		/* size of dd_desc */
	struct ath_buf *dd_bufptr;	/* associated buffers */
};

struct ath_hal;
struct ath_desc;
struct ath_ratectrl;
struct ath_tx99;
struct proc_dir_entry;

/*
 * Data transmit queue state.  One of these exists for each
 * hardware transmit queue.  Packets sent to us from above
 * are assigned to queues based on their priority.  Not all
 * devices support a complete set of hardware transmit queues.
 * For those devices the array sc_ac2q will map multiple
 * priorities to fewer hardware queues (typically all to one
 * hardware queue).
 */
struct ath_txq {
	u_int axq_qnum;			/* hardware q number */
	u_int32_t *axq_link;		/* link ptr in last TX desc */
	STAILQ_HEAD(, ath_buf) axq_q;	/* transmit queue */
	spinlock_t axq_lock;		/* lock on q and link */
	int axq_depth;			/* queue depth */
	u_int32_t axq_totalqueued;	/* total ever queued */
	u_int axq_intrcnt;		/* count to determine if descriptor
					 * should generate int on this txq.
					 */
	/*
	 * Staging queue for frames awaiting a fast-frame pairing.
	 */
	TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq;

        /* scratch compression buffer */
        char *axq_compbuf;		/* scratch comp buffer */
        dma_addr_t axq_compbufp;	/* scratch comp buffer (phys)*/
        u_int axq_compbufsz;		/* scratch comp buffer size */
};

/* driver-specific vap state */
struct ath_vap {
	struct ieee80211vap av_vap;	/* base class */
	int (*av_newstate)(struct ieee80211vap *, enum ieee80211_state, int);
	/* XXX beacon state */
	struct ath_buf *av_bcbuf;	/* beacon buffer */
	struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
	int av_bslot;			/* beacon slot index */
	struct ath_txq av_mcastq;	/* multicast transmit queue */
	u_int8_t	av_dfswait_run;
};
#define	ATH_VAP(_v)	((struct ath_vap *)(_v))

#define	ATH_BEACON_AIFS_DEFAULT		0  /* Default aifs for ap beacon q */
#define	ATH_BEACON_CWMIN_DEFAULT	0  /* Default cwmin for ap beacon q */
#define	ATH_BEACON_CWMAX_DEFAULT	0  /* Default cwmax for ap beacon q */

#define ATH_TXQ_INTR_PERIOD		5  /* axq_intrcnt period for intr gen */
#define	ATH_TXQ_LOCK_INIT(_tq)		spin_lock_init(&(_tq)->axq_lock)
#define	ATH_TXQ_LOCK_DESTROY(_tq)	
#define	ATH_TXQ_LOCK(_tq)		spin_lock(&(_tq)->axq_lock)
#define	ATH_TXQ_UNLOCK(_tq)		spin_unlock(&(_tq)->axq_lock)
#define	ATH_TXQ_LOCK_BH(_tq)		spin_lock_bh(&(_tq)->axq_lock)
#define	ATH_TXQ_UNLOCK_BH(_tq)		spin_unlock_bh(&(_tq)->axq_lock)
#define ATH_TXQ_LOCK_IRQ(_tq)		do {	\
	unsigned long __axq_lockflags;		\
	spin_lock_irqsave(&(_tq)->axq_lock, __axq_lockflags);
#define ATH_TXQ_UNLOCK_IRQ(_tq)			\
	spin_unlock_irqrestore(&(_tq)->axq_lock, __axq_lockflags); \
} while (0)
#define ATH_TXQ_UNLOCK_IRQ_EARLY(_tq)			\
	spin_unlock_irqrestore(&(_tq)->axq_lock, __axq_lockflags);

#define ATH_TXQ_UAPSDQ_LOCK_IRQ(_tq)	spin_lock_irqsave(&(_tq)->axq_lock, uapsdq_lockflags)
#define ATH_TXQ_UAPSDQ_UNLOCK_IRQ(_tq)	spin_unlock_irqrestore(&(_tq)->axq_lock, uapsdq_lockflags)




#define	ATH_TXQ_LOCK_ASSERT(_tq) \
	KASSERT(spin_is_locked(&(_tq)->axq_lock), ("txq not locked!"))
#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
	STAILQ_INSERT_TAIL( &(_tq)->axq_q, (_elm), _field); \
	(_tq)->axq_depth++; \
	(_tq)->axq_totalqueued++; \
} while (0)
#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
	STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
	(_tq)->axq_depth--; \
} while (0)
/* move buffers from MCASTQ to CABQ */
#define ATH_TXQ_MOVE_MCASTQ(_tqs,_tqd) do { \
	(_tqd)->axq_depth += (_tqs)->axq_depth; \
	(_tqd)->axq_totalqueued += (_tqs)->axq_totalqueued; \
	(_tqd)->axq_link = (_tqs)->axq_link; \
	STAILQ_CONCAT(&(_tqd)->axq_q,&(_tqs)->axq_q); \
	(_tqs)->axq_depth=0; \
	(_tqs)->axq_totalqueued = 0; \
	(_tqs)->axq_link = NULL; \
} while (0)

/* 
 * concat buffers from one queue to other
 */
#define ATH_TXQ_MOVE_Q(_tqs,_tqd)  ATH_TXQ_MOVE_MCASTQ(_tqs,_tqd)

#define	BSTUCK_THRESH	3	/* # of stuck beacons before resetting NB: this is a guess*/

struct ath_softc {
	struct ieee80211com sc_ic;		/* NB: must be first */
	struct net_device *sc_dev;
	struct semaphore sc_lock;		/* dev-level lock */
	struct net_device_stats	sc_devstats;	/* device statistics */
	struct ath_stats	sc_stats;		/* private statistics */
	int devid;
	int sc_debug;
	void (*sc_recv_mgmt)(struct ieee80211_node *, struct sk_buff *, int, int, u_int32_t);
	void (*sc_node_cleanup)(struct ieee80211_node *);
	void (*sc_node_free)(struct ieee80211_node *);
	void *sc_bdev;				/* associated bus device */
	struct ath_hal *sc_ah;			/* Atheros HAL */
	struct ath_ratectrl *sc_rc;		/* tx rate control support */
	struct ath_tx99 *sc_tx99; 		/* tx99 support */
	void (*sc_setdefantenna)(struct ath_softc *, u_int);
	unsigned int 	sc_invalid:1,		/* being detached */
			sc_mrretry:1,		/* multi-rate retry support */
			sc_softled:1,		/* enable LED gpio status */
			sc_splitmic:1,		/* split TKIP MIC keys */
			sc_needmib:1,		/* enable MIB stats intr */
			sc_hasdiversity:1,	/* rx diversity available */
			sc_diversity:1, 	/* enable rx diversity */
			sc_olddiversity:1, 	/* diversity setting before XR enable */	       
			sc_hasveol:1,		/* tx VEOL support */
			sc_hastpc:1,		/* per-packet TPC support */
			sc_dturbo:1,		/* dynamic turbo capable */
			sc_dturbo_switch:1,	/* turbo switch mode*/
			sc_dturbo_hold:1,	/* dynamic turbo hold state */
			sc_rate_recn_state:1,	/* dynamic turbo state recmded by ratectrl */
			sc_ignore_ar:1,		/* ignore AR during transision*/
			sc_ledstate:1,		/* LED on/off state */
			sc_blinking:1,		/* LED blink operation active */
			sc_beacons:1,		/* beacons running */
			sc_hasbmask:1,		/* bssid mask support */
			sc_mcastkey:1,		/* mcast key cache search */
			sc_hastsfadd:1,		/* tsf adjust support */
			sc_scanning:1,		/* scanning active */
			sc_nostabeacons:1,	/* no beacons for station */
			sc_xrgrppoll:1,		/* xr group polls are active */
			sc_syncbeacon:1,	/* sync/resync beacon timers */
			sc_hasclrkey:1,		/* CLR key supported */
			sc_devstopped:1,	/* stopped due to of no tx bufs */
			sc_stagbeacons:1,	/* use staggered beacons */
			sc_rtasksched:1, 	/* radar task is scheduled */
			sc_dfswait:1,    	/* waiting on channel for radar detect */
			sc_dfstest:1,		/* Test timer in progress */
		        sc_ackrate:1;           /* send acks at high bitrate */
	/* rate tables */
	const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
	const HAL_RATE_TABLE *sc_currates;	/* current rate table */
	const HAL_RATE_TABLE *sc_xr_rates;	/* XR rate table */
	const HAL_RATE_TABLE *sc_half_rates;	/* half rate table */
	const HAL_RATE_TABLE *sc_quarter_rates;	/* quarter rate table */
	HAL_OPMODE sc_opmode;			/* current hal operating mode */
	enum ieee80211_phymode sc_curmode;	/* current phy mode */
	u_int16_t sc_curtxpow;			/* current tx power limit */
	u_int16_t sc_curaid;			/* current association id */
	HAL_CHANNEL sc_curchan;			/* current h/w channel */
	u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
	u_int8_t	sc_rixmap[256];			/* IEEE to h/w rate table ix */
	struct {
		u_int8_t	ieeerate;		/* IEEE rate */
		u_int8_t	flags;			/* radiotap flags */
		u_int16_t ledon;			/* softled on time */
		u_int16_t ledoff;		/* softled off time */
	} sc_hwmap[32];				/* h/w rate ix mappings */
	u_int8_t sc_minrateix;			/* min h/w rate index */
	u_int8_t sc_protrix;			/* protection rate index */
	u_int8_t sc_mcastantenna;		/* Multicast antenna number */
	u_int8_t sc_txantenna;			/* data tx antenna (fixed or auto) */
	u_int8_t sc_dfstest_ieeechan;		/* IEEE channel number to return to after a dfs mute test */
	u_int32_t sc_dfstesttime;		/* Time to stay off chan during dfs test */
	u_int16_t sc_nvaps;			/* # of active virtual ap's */
	u_int8_t sc_nstavaps;			/* # of active station vaps */
	u_int8_t sc_nmonvaps;			/* # of monitor vaps */
	u_int8_t sc_nbcnvaps;			/* # of vaps sending beacons */
	u_int sc_fftxqmin;			/* aggregation threshold */
	HAL_INT sc_imask;			/* interrupt mask copy */
	u_int sc_keymax;				/* size of key cache */
	u_int8_t sc_keymap[ATH_KEYBYTES];	/* key use bit map */
	struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */
	u_int8_t sc_bssidmask[IEEE80211_ADDR_LEN];

	u_int sc_ledpin;				/* GPIO pin for driving LED */
	u_int sc_ledon;				/* pin setting for LED on */
	u_int sc_ledidle;			/* idle polling interval */
	int sc_ledevent;				/* time of last LED event */
	u_int8_t sc_rxrate;			/* current rx rate for LED */
	u_int8_t sc_txrate;			/* current tx rate for LED */
	u_int16_t sc_ledoff;			/* off time for current blink */
	struct timer_list sc_ledtimer;		/* led off timer */
	struct timer_list sc_dfswaittimer;	/* dfs wait timer */
	struct timer_list sc_dfstesttimer;	/* dfs mute test timer */

	struct ATH_TQ_STRUCT sc_fataltq;	/* fatal error intr tasklet */

	int sc_rxbufsize;			/* rx size based on mtu */
	struct ath_descdma sc_rxdma;		/* RX descriptors */
	ath_bufhead sc_rxbuf;			/* receive buffer */
	struct ath_buf *sc_rxbufcur;		/* current rx buffer */
	u_int32_t *sc_rxlink;			/* link ptr in last RX desc */
	spinlock_t sc_rxbuflock; 
	struct ATH_TQ_STRUCT sc_rxtq;		/* rx intr tasklet */
	struct ATH_TQ_STRUCT sc_rxorntq;	/* rxorn intr tasklet */
	u_int8_t sc_defant;			/* current default antenna */
	u_int8_t sc_rxotherant;			/* rx's on non-default antenna*/
	u_int16_t sc_cachelsz;			/* cache line size */

	struct ath_descdma sc_txdma;		/* TX descriptors */
	ath_bufhead sc_txbuf;			/* transmit buffer */
	spinlock_t sc_txbuflock;		/* txbuf lock */
	u_int sc_txqsetup;			/* h/w queues setup */
	u_int sc_txintrperiod;			/* tx interrupt batching */
	struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
	struct ath_txq *sc_ac2q[WME_NUM_AC];	/* WME AC -> h/w qnum */ 
	struct ATH_TQ_STRUCT sc_txtq;		/* tx intr tasklet */
	u_int8_t sc_grppoll_str[GRPPOLL_RATE_STR_LEN];  
	struct ath_descdma sc_bdma;		/* beacon descriptors */
	ath_bufhead sc_bbuf;			/* beacon buffers */
	u_int sc_bhalq;				/* HAL q for outgoing beacons */
	u_int sc_bmisscount;			/* missed beacon transmits */
	u_int32_t sc_ant_tx[8];			/* recent tx frames/antenna */
	struct ath_txq *sc_cabq;			/* tx q for cab frames */
	struct ath_txq sc_grpplq;		/* tx q for XR group polls */
	struct ath_txq *sc_xrtxq;		/* tx q for XR data */
	struct ath_descdma sc_grppolldma;	/* TX descriptors for grppoll */
	ath_bufhead sc_grppollbuf;		/* transmit buffers for grouppoll  */
	u_int16_t sc_xrpollint;			/* xr poll interval */
	u_int16_t sc_xrpollcount;		/* xr poll count */
	struct ath_txq *sc_uapsdq;		/* tx q for uapsd */
	struct ATH_TQ_STRUCT sc_bmisstq;	/* bmiss intr tasklet */
	struct ATH_TQ_STRUCT sc_bstucktq;	/* beacon stuck intr tasklet */
	enum {
		OK,				/* no change needed */
		UPDATE,				/* update pending */
		COMMIT				/* beacon sent, commit change */
	} sc_updateslot;			/* slot time update fsm */
	int sc_slotupdate;			/* slot to next advance fsm */
	struct ieee80211vap *sc_bslot[ATH_BCBUF];/* beacon xmit slots */
	int sc_bnext;				/* next slot for beacon xmit */

	struct timer_list sc_cal_ch;		/* calibration timer */
	HAL_NODE_STATS sc_halstats;		/* station-mode rssi stats */
	struct ATH_WORK_THREAD sc_radartask;	/* Schedule task for DFS handling */

#ifdef CONFIG_SYSCTL
	struct ctl_table_header *sc_sysctl_header;
	struct ctl_table *sc_sysctls;
#endif

	u_int16_t sc_reapcount;  		/* # of tx buffers reaped after net dev stopped */

#ifdef ATH_SUPERG_DYNTURBO
	struct timer_list sc_dturbo_switch_mode;/* AP scan timer */
	u_int32_t sc_dturbo_tcount;		/* beacon intval count */
	u_int32_t sc_dturbo_hold_max;		/* hold count before switching to base*/
	u_int16_t sc_dturbo_hold_count;		/* hold count before switching to base*/
	u_int16_t sc_dturbo_turbo_tmin;		/* min turbo count */
	u_int32_t sc_dturbo_bytes;		/* bandwidth stats */ 
	u_int32_t sc_dturbo_base_tmin;		/* min time in base */
	u_int32_t sc_dturbo_turbo_tmax;		/* max time in turbo */
	u_int32_t sc_dturbo_bw_base;		/* bandwidth threshold */
	u_int32_t sc_dturbo_bw_turbo;		/* bandwidth threshold */
#endif
	u_int sc_slottimeconf;			/* manual override for slottime */
};

typedef void (*ath_callback) (struct ath_softc *);
#define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))

#define	ATH_TXBUF_LOCK_INIT(_sc)	spin_lock_init(&(_sc)->sc_txbuflock)
#define	ATH_TXBUF_LOCK_DESTROY(_sc)
#define	ATH_TXBUF_LOCK(_sc)		spin_lock(&(_sc)->sc_txbuflock)
#define	ATH_TXBUF_UNLOCK(_sc)		spin_unlock(&(_sc)->sc_txbuflock)