mottsecdrv.h

freescale mottsec 千兆单元驱动源码

#define ZXR10_MOT_TSEC_IEVENT_REG          tsecReg->ievent
#define ZXR10_MOT_TSEC_IMASK_REG           tsecReg->imask
#define ZXR10_MOT_TSEC_EDIS_REG            tsecReg->edis
#define ZXR10_MOT_TSEC_ECNTRL_REG          tsecReg->ecntrl
#define ZXR10_MOT_TSEC_MINFLR_REG          tsecReg->minflr
#define ZXR10_MOT_TSEC_PTV_REG             tsecReg->ptv
#define ZXR10_MOT_TSEC_DMACTRL_REG         tsecReg->dmactrl
#define ZXR10_MOT_TSEC_TBIPA_REG           tsecReg->tbipa
#define ZXR10_MOT_TSEC_FIFO_TX_THR_REG     tsecReg->fifoTxTheshold
#define ZXR10_MOT_TSEC_FIFO_TX_STARVE_REG  tsecReg->fifoTxStarve
#define ZXR10_MOT_TSEC_FIFO_TX_STARVE_SHUTOFF_REG tsecReg->fifoTxStarveShutoff
#define ZXR10_MOT_TSEC_TCTRL_REG           tsecReg->tctrl
#define ZXR10_MOT_TSEC_TSTAT_REG           tsecReg->tstat
#define ZXR10_MOT_TSEC_TBDLEN_REG          tsecReg->tbdlen
#define ZXR10_MOT_TSEC_TXIC_REG            tsecReg->txic
#define ZXR10_MOT_TSEC_CTBPTR_REG          tsecReg->ctbptr
#define ZXR10_MOT_TSEC_TBPTR_REG           tsecReg->tbptr
#define ZXR10_MOT_TSEC_TBASE_REG           tsecReg->tbase
#define ZXR10_MOT_TSEC_OSTBD_REG           tsecReg->ostbd
#define ZXR10_MOT_TSEC_OSTBDP_REG          tsecReg->ostbdp
#define ZXR10_MOT_TSEC_RCTRL_REG           tsecReg->rctrl
#define ZXR10_MOT_TSEC_RSTAT_REG           tsecReg->rstat
#define ZXR10_MOT_TSEC_RBDLEN_REG          tsecReg->rbdlen
#define ZXR10_MOT_TSEC_CRBPTR_REG          tsecReg->crbptr
#define ZXR10_MOT_TSEC_MRBLR_REG           tsecReg->mrblr
#define ZXR10_MOT_TSEC_RBPTR_REG           tsecReg->rbptr
#define ZXR10_MOT_TSEC_RBASE_REG           tsecReg->rbase
#define ZXR10_MOT_TSEC_MACCFG1_REG         tsecReg->maccfg1
#define ZXR10_MOT_TSEC_MACCFG2_REG         tsecReg->maccfg2
#define ZXR10_MOT_TSEC_IPGIFG_REG          tsecReg->ipgifgi
#define ZXR10_MOT_TSEC_HAFDUP_REG          tsecReg->hafdup
#define ZXR10_MOT_TSEC_MAXFRM_REG          tsecReg->maxfrm
#define ZXR10_MOT_TSEC_MIIMCFG_REG         tsecMiiReg->miicfg
#define ZXR10_MOT_TSEC_MIIMCOM_REG         tsecMiiReg->miicom
#define ZXR10_MOT_TSEC_MIIMADD_REG         tsecMiiReg->miimadd
#define ZXR10_MOT_TSEC_MIIMCON_REG         tsecMiiReg->miimcon
#define ZXR10_MOT_TSEC_MIIMSTAT_REG        tsecMiiReg->miimstat
#define ZXR10_MOT_TSEC_MIIMIND_REG         tsecMiiReg->miimind
#define ZXR10_MOT_TSEC_IFSTAT_REG          tsecReg->ifstat
#define ZXR10_MOT_TSEC_MACSTNADDR1_REG     tsecReg->macstnaddr1
#define ZXR10_MOT_TSEC_MACSTNADDR2_REG     tsecReg->macstnaddr2
#define ZXR10_MOT_TSEC_TR64_REG            tsecReg->tr64
#define ZXR10_MOT_TSEC_TR127_REG           tsecReg->tr127
#define ZXR10_MOT_TSEC_TR255_REG           tsecReg->tr255
#define ZXR10_MOT_TSEC_TR511_REG           tsecReg->tr511
#define ZXR10_MOT_TSEC_TR1K_REG            tsecReg->tr1k
#define ZXR10_MOT_TSEC_TRMAX_REG           tsecReg->trmax
#define ZXR10_MOT_TSEC_TRMGV_REG           tsecReg->trmgv
#define ZXR10_MOT_TSEC_RBYT_REG            tsecReg->rbyt
#define ZXR10_MOT_TSEC_RPKT_REG            tsecReg->rpkt
#define ZXR10_MOT_TSEC_RFCS_REG            tsecReg->rfcs
#define ZXR10_MOT_TSEC_RMCA_REG            tsecReg->rmca
#define ZXR10_MOT_TSEC_RBCA_REG            tsecReg->rbca
#define ZXR10_MOT_TSEC_RXCF_REG            tsecReg->rxcf
#define ZXR10_MOT_TSEC_RXPF_REG            tsecReg->rxpf
#define ZXR10_MOT_TSEC_RXUO_REG            tsecReg->rxuo
#define ZXR10_MOT_TSEC_RALN_REG            tsecReg->raln
#define ZXR10_MOT_TSEC_RFLR_REG            tsecReg->rflr
#define ZXR10_MOT_TSEC_RCDE_REG            tsecReg->rcde
#define ZXR10_MOT_TSEC_RCSE_REG            tsecReg->rcse
#define ZXR10_MOT_TSEC_RUND_REG            tsecReg->rund
#define ZXR10_MOT_TSEC_ROVR_REG            tsecReg->rovr
#define ZXR10_MOT_TSEC_RFGR_REG            tsecReg->rfgr
#define ZXR10_MOT_TSEC_RJBR_REG            tsecReg->rjbr
#define ZXR10_MOT_TSEC_RDRP_REG            tsecReg->rdrp

#define ZXR10_MOT_TSEC_TBYT_REG            tsecReg->tbyt
#define ZXR10_MOT_TSEC_TPKT_REG            tsecReg->tpkt
#define ZXR10_MOT_TSEC_TMCA_REG            tsecReg->tmca
#define ZXR10_MOT_TSEC_TBCA_REG            tsecReg->tbca
#define ZXR10_MOT_TSEC_TXPF_REG            tsecReg->txpf
#define ZXR10_MOT_TSEC_TDFR_REG            tsecReg->tdfr
#define ZXR10_MOT_TSEC_TEDF_REG            tsecReg->tedf
#define ZXR10_MOT_TSEC_TSCL_REG            tsecReg->tscl
#define ZXR10_MOT_TSEC_TMCL_REG            tsecReg->tmcl
#define ZXR10_MOT_TSEC_TLCL_REG            tsecReg->tlcl
#define ZXR10_MOT_TSEC_TXCL_REG            tsecReg->txcl
#define ZXR10_MOT_TSEC_TNCL_REG            tsecReg->tncl

#define ZXR10_MOT_TSEC_TDRP_REG            tsecReg->tdrp
#define ZXR10_MOT_TSEC_TJBR_REG            tsecReg->tjbr
#define ZXR10_MOT_TSEC_TFCS_REG            tsecReg->tfcs
#define ZXR10_MOT_TSEC_TFCF_REG            tsecReg->tfcf
#define ZXR10_MOT_TSEC_TOVR_REG            tsecReg->tovr
#define ZXR10_MOT_TSEC_TUND_REG            tsecReg->tund
#define ZXR10_MOT_TSEC_TFGR_REG            tsecReg->tfrg

#define ZXR10_MOT_TSEC_CAR1_REG            tsecReg->car1
#define ZXR10_MOT_TSEC_CAR2_REG            tsecReg->car2
#define ZXR10_MOT_TSEC_CAM1_REG            tsecReg->cam1
#define ZXR10_MOT_TSEC_CAM2_REG            tsecReg->cam2

#define ZXR10_MOT_TSEC_IADDR_REG           tsecReg->iaddr
#define ZXR10_MOT_TSEC_IADDR0_REG          tsecReg->iaddr[0]
#define ZXR10_MOT_TSEC_IADDR1_REG          tsecReg->iaddr[1]
#define ZXR10_MOT_TSEC_IADDR2_REG          tsecReg->iaddr[2]
#define ZXR10_MOT_TSEC_IADDR3_REG          tsecReg->iaddr[3]
#define ZXR10_MOT_TSEC_IADDR4_REG          tsecReg->iaddr[4]
#define ZXR10_MOT_TSEC_IADDR5_REG          tsecReg->iaddr[5]
#define ZXR10_MOT_TSEC_IADDR6_REG          tsecReg->iaddr[6]
#define ZXR10_MOT_TSEC_IADDR7_REG          tsecReg->iaddr[7]

#define ZXR10_MOT_TSEC_GADDR_REG           tsecReg->gaddr
#define ZXR10_MOT_TSEC_GADDR0_REG          tsecReg->gaddr[0]
#define ZXR10_MOT_TSEC_GADDR1_REG          tsecReg->gaddr[1]
#define ZXR10_MOT_TSEC_GADDR2_REG          tsecReg->gaddr[2]
#define ZXR10_MOT_TSEC_GADDR3_REG          tsecReg->gaddr[3]
#define ZXR10_MOT_TSEC_GADDR4_REG          tsecReg->gaddr[4]
#define ZXR10_MOT_TSEC_GADDR5_REG          tsecReg->gaddr[5]
#define ZXR10_MOT_TSEC_GADDR6_REG          tsecReg->gaddr[6]
#define ZXR10_MOT_TSEC_GADDR7_REG          tsecReg->gaddr[7]

#define ZXR10_MOT_TSEC_ATTR_REG            tsecReg->attr
#define ZXR10_MOT_TSEC_ATTRELI_REG         tsecReg->attreli

/* TBI registers */
#define ZXR10_MOT_TSEC_TBI_SR_REG          ZXR10_MOT_TSEC_TBIPA_REG + 1


/* Driver State Variables */
#define ZXR10_MOT_TSEC_STATE_LOADED        0x01
#define ZXR10_MOT_TSEC_STATE_RUNNING       0x02

/* Internal driver flags */

#define ZXR10_MOT_TSEC_OWN_BUF_MEM    0x01    /* internally provided memory for data*/
#define ZXR10_MOT_TSEC_INV_TBD_NUM    0x02    /* invalid tbdNum provided */
#define ZXR10_MOT_TSEC_INV_RBD_NUM    0x04    /* invalid rbdNum provided */
#define ZXR10_MOT_TSEC_POLLING        0x08    /* polling mode */
#define ZXR10_MOT_TSEC_PROM           0x20    /* promiscuous mode */
#define ZXR10_MOT_TSEC_MCAST          0x40    /* multicast addressing mode */
#define ZXR10_MOT_TSEC_FD             0x80    /* full duplex mode */
#define ZXR10_MOT_TSEC_OWN_BD_MEM     0x10    /* internally provided memory for BDs */
#define ZXR10_MOT_TSEC_MIN_TX_PKT_SZ   100     /* the smallest packet we send */

#define ZXR10_MOT_TSEC_CL_NUM_DEFAULT   128   /* number of tx clusters */
#define ZXR10_MOT_TSEC_CL_MULTIPLE       11    /* ratio of clusters to RBDs */
#define ZXR10_MOT_TSEC_TBD_NUM_DEFAULT  32    /* default number of TBDs */
#define ZXR10_MOT_TSEC_RBD_NUM_DEFAULT  32    /* default number of RBDs */
#define ZXR10_MOT_TSEC_TX_POLL_NUM      1     /* one TBD for poll operation */

#define ZXR10_MOT_TSEC_CL_OVERHEAD      4     /* prepended cluster overhead */
#define ZXR10_MOT_TSEC_CL_ALIGNMENT     64    /* cluster required alignment */
#define ZXR10_MOT_TSEC_CL_SIZE          1536  /* cluster size */
#define ZXR10_MOT_TSEC_MBLK_ALIGNMENT   64    /* mBlks required alignment */
#define ZXR10_MOT_TSEC_BD_SIZE          0x8   /* size of TSEC BD */
#define ZXR10_MOT_TSEC_BD_ALIGN         64   /* required alignment for BDs */
#define ZXR10_MOT_TSEC_BUF_ALIGN        64   /* required alignment for data buffer */
/*
 * the total is 0x630 and it accounts for the required alignment
 * of receive data buffers, and the cluster overhead.
 */
#define XXX_TSEC_MAX_CL_LEN ((MII_ETH_MAX_PCK_SZ             \
                            + (ZXR10_MOT_TSEC_BUF_ALIGN - 1)       \
                            + ZXR10_MOT_TSEC_BUF_ALIGN             \
                            + (ZXR10_MOT_TSEC_CL_OVERHEAD - 1))    \
                            & (~ (ZXR10_MOT_TSEC_CL_OVERHEAD - 1)))

#define ZXR10_MOT_TSEC_MAX_CL_LEN     ROUND_UP(XXX_TSEC_MAX_CL_LEN,ZXR10_MOT_TSEC_BUF_ALIGN)

#define ZXR10_MOT_TSEC_RX_CL_SZ       (ZXR10_MOT_TSEC_MAX_CL_LEN)
#define ZXR10_MOT_TSEC_TX_CL_SZ       (ZXR10_MOT_TSEC_MAX_CL_LEN)

/* BIT mask defines for hardware specific PHY events. */
#define ZXR10_MOT_TSEC_PHY_EVENT_AUTONEG_ERROR    0x0001
#define ZXR10_MOT_TSEC_PHY_EVENT_SPEED            0x0002
#define ZXR10_MOT_TSEC_PHY_EVENT_DUPLEX           0x0004
#define ZXR10_MOT_TSEC_PHY_EVENT_AUTONEG_COMPLETE 0x0008
#define ZXR10_MOT_TSEC_PHY_EVENT_LINK             0x0010
#define ZXR10_MOT_TSEC_PHY_EVENT_SYMBOL_ERROR     0x0020
#define ZXR10_MOT_TSEC_PHY_EVENT_FALSE_CARRIER    0x0040
#define ZXR10_MOT_TSEC_PHY_EVENT_FIFO_ERROR       0x0080
#define ZXR10_MOT_TSEC_PHY_EVENT_XOVER            0x0100
#define ZXR10_MOT_TSEC_PHY_EVENT_DOWNSHIFT        0x0200
#define ZXR10_MOT_TSEC_PHY_EVENT_POLARITY         0x0400
#define ZXR10_MOT_TSEC_PHY_EVENT_JABBER           0x0800

/* PHY Access definitions */
#define ZXR10_MOT_TSEC_PHY_GIG_STATUS_REG	0xa
#define ZXR10_MOT_TSEC_PHY_1000_M_LINK_FD     0x0800
#define ZXR10_MOT_TSEC_PHY_1000_M_LINK_OK     0x1000

#define ZXR10_MOT_TSEC_PHY_LINK_STATUS        0x5
#define ZXR10_MOT_TSEC_PHY_10_M_LINK_FD       0x0040
#define ZXR10_MOT_TSEC_PHY_100_M_LINK_FD      0x0100

typedef struct
    {
    UINT8  autonegError;            /* 0-N/A, 0 - none,   1- error */
    UINT8  duplex;                  /* 1 - half,   2- full */
#define ZXR10_MOT_TSEC_PHY_DUPLEX_HALF    (1)
#define ZXR10_MOT_TSEC_PHY_DUPLEX_FULL    (2)
    UINT8  speed;                   /* 0-N/A, 1 - 10, 2- 100, 3 -1G */
#define ZXR10_MOT_TSEC_PHY_SPEED_10       (1)
#define ZXR10_MOT_TSEC_PHY_SPEED_100      (2)
#define ZXR10_MOT_TSEC_PHY_SPEED_1000     (3)
    UINT8  link;                    /* 0-N/A, 1 - down, 2- up */
    UINT8  symbolError;             /* 0-N/A, 1 - none, 2- error */
    UINT8  autoNegComplete;         /* 0-N/A, 1 - no, 2- completed */
    UINT8  energyDetect;            /* 0-N/A, 1 - no, 2- detected */
    UINT8  falseCarrier;            /* 0-N/A, 1 - no, 2- detected */
    UINT8  downShift;               /* 0-N/A, 1 - no, 2- detected */
    UINT8  fifoError;               /* 0-N/A, 1 - none, 2- error */
    UINT8  xover;                   /* 0-N/A, 1 - MDI, 2- MDIX */
    UINT8  polarity;                /* 0-N/A, 1 - normal, 2- reversed */
    UINT8  jabber;                  /* 0-N/A, 1 - no, 2- detected */
    UINT8  pageReceived;            /* 0-N/A, 1 - no, 2- detected */
    UINT8  cableLength;             /* 0-N/A */
    UINT8  txPause;                 /* 0-N/A, 1 - no, 2- detected */
    UINT8  rxPause;                 /* 0-N/A, 1 - no, 2- detected */
    UINT8  farEndFault;             /* 0-N/A, 1 - no, 2- detected */
    UINT32 rxErrorCntr;             /* 0-N/A, number of rx errors */
    UINT32 reserved[4];             /* future use */
    } ZXR10_MOT_TSEC_PHY_STATUS;

typedef struct tsec_multi_addr
{
    struct tsec_multi_addr * pNext;
    unsigned char enetAddr[6];
    unsigned char reserved[2]; /* for byte align */
}TSEC_MULTI_ADDR;
/* The definition of the driver control structure */

typedef struct tsec_drv_ctrl
    {
    DRV_VIR_CTRL  drvCtrl;
    SEM_ID        drvSem;
    UINT32        globalPort;
    int           vecRxNum;
    int           vecTxNum;
    int           vecErrNum;
    void *        net;

        /* Bsp specific functions and call backs */
    FUNCPTR       intConnect;
    FUNCPTR       intDisConnect;
    FUNCPTR       intEnable;
    FUNCPTR       intDisable;
    FUNCPTR       enetEnable;      /* enable ethernet */
    FUNCPTR       enetDisable;     /* disable ethernet */
    FUNCPTR       miiPhyRead;      /* mii Read */
    FUNCPTR       miiPhyWrite;     /* mii Write */

    FUNCPTR       initMacAddrGet;

    /* Phy specific functions and call backs */
    FUNCPTR       phyInitFunc;         /* BSP Phy Init */
    FUNCPTR       phyStatusFunc;       /* Status Get function */
    /* Mac specific functions and call backs */
    FUNCPTR       extWriteL2AllocFunc; /* Use ext write alloc L2 for Tx BD */

    unsigned char enetAddr[6]; /* current Ethernet Address */
    unsigned char reserved[2]; /* for byte align */
    TSEC_MULTI_ADDR * multiAddPtr;

    TSEC_REG_T *  tsecRegsPtr; /* pointer to TSEC registers */
    UINT32        initFlags;   /* user init flags */
    UINT32        userFlags;

    UINT32        maxRxFrames; /* max frames to Receive in one job */

    volatile BOOL rxJobQued;
    volatile BOOL tbdFreeQued;
    volatile UINT32 txHandlerQued;
    volatile BOOL phyIntQued;
    
    UINT32   bakMaccfg2Reg;
    UINT32   bakMacStnAddr1Reg;
    UINT32   bakMacStnAddr2Reg;
    /* phy init parameter table */
    UINT32   phyAddr;
    /* Driver specific init parameters */
    ZXR10_MOT_TSEC_PARAMS     * initParms;

    /* TSEC hardware specific init parameters */
    ZXR10_MOT_TSEC_EXT_PARAMS * initParmsExt;

    TSEC_REG_T * tsecMiiPtr;    /* pointer to TSEC Mii registers */

    UINT32      fifoTxBase;     /* address of Tx FIFO in internal RAM */
    UINT32      fifoRxBase;     /* address of Rx FIFO in internal RAM */

    char      * pBufAlloc;      /* Allocated TSEC memory pool base */
    char      * pBufBase;       /* Rounded TSEC memory pool base */
    UINT32      bufSize;        /* TSEC memory pool size */

    TSEC_BD   * pBdAlloc;       /* TSEC BDs Alloc pointer */
    TSEC_BD   * pBdBase;        /* TSEC BDs base */
    UINT32      bdSize;         /* TSEC BDs size */

    /* receive buffer descriptor management */
    UINT32      rbdNum;          /* number of TX bd's */
    TSEC_BD   * pRbdNext;        /* RBD next to rx */
    TSEC_BD   * pRbdLast;        /* RBD last to replenish */
    UINT32      rbdCnt;          /* number of rbds full */
    TSEC_BD   * pRbdBase;        /* RBD ring */
    UINT32      rbdIndex;
    UINT32      rbdMask;
    UINT32      rxUnStallThresh; /* rx reclaim threshold */
    UINT32      rxStallThresh;   /* rx low water threshold */

    volatile BOOL rxStall;       /* rx handler stalled - no Tbd */

    /* transmit buffer descriptor management */

    UINT32      tbdNum;          /* number of TX bd's */
    volatile TSEC_BD   * pTbdNext;        /* TBD index */
    TSEC_BD   * pTbdLast;        /* TBD index */
    UINT32      tbdFree;
    TSEC_BD   * pTbdBase;        /* TBD ring base */
    char     ** tBufList;        /* allocated clusters */
    UINT32      tbdMask;
    UINT32      tbdIndex;
    UINT32      tbdCleanIndex;
    UINT16      txUnStallThresh; /* tx reclaim threshold */
    UINT16      txStallThresh;   /* tx low water threshold */

    UINT32      tbiAdr;          /* tbi interface address */
    UINT32      phyFlags;       /* Phy flags */
    UINT32      flags;          /* driver flags */
    UINT32      state;          /* driver state including load flag */
    UINT32      intMask;        /* interrupt mask register */
    UINT32      intErrorMask;   /* interrupt error mask register */
    UCHAR *     pTxPollBuf;     /* cluster pointer for poll mode */
    M_BLK_ID    pTxPollMblk;
                                 /* transmit command */
    char       * pClBlkArea;     /* cluster block pointer */
    UINT32       clBlkSize;      /* clusters block memory size */
    UINT32       mBlkSize;       /* mBlocks area memory size */
    CACHE_FUNCS  bufCacheFuncs;  /* cache descriptor */
    CL_POOL_ID    pClPoolId;      /* cluster pool identifier */
    DRV_VIR_PHY * phyInfo;        /* info on a MII-compliant PHY */

    BOOL         lscHandling;
    BOOL         txStall;       /* tx handler stalled - no Tbd */

    /* function pointers to support unit testing */

    FUNCPTR     netJobAdd;
    FUNCPTR     muxTxRestart;
    FUNCPTR     muxError;


#ifdef ZXR10_MOT_TSEC_DBG
    TSEC_DRIVER_STATS *stats;
#endif
    UINT32 missedCnt;
    UINT32 passCnt;
    UINT32 packetCnt;
    UINT32 starveCnt;
    UINT32 busyMissed;
    BOOL   busyState;
    END_IFDRVCONF endStatsConf;
    END_IFCOUNTERS endStatsCounters;

    } TSEC_DRV_CTRL;

typedef struct 
    {
    int len;		/* Length of table in bytes. */
    char *pTable;		/* Pointer to entries. */
    } MOT_MULTI_TABLE;
    
IMPORT STATUS cacheInvalidate (CACHE_TYPE, void *, size_t);
IMPORT STATUS cacheFlush (CACHE_TYPE, void *, size_t);
IMPORT int    intEnable (int);
IMPORT int    intDisable (int);

#ifdef __cplusplus
}
#endif

#endif /* __INCzxr10_motTsecEndh */