mottsecdrv.h

freescale mottsec 千兆单元驱动源码

                 ZXR10_MOT_TSEC_MACCFG2_PADCRC      | \
                 ZXR10_MOT_TSEC_MACCFG2_CRC_EN      | \
                 ZXR10_MOT_TSEC_MACCFG2_IF_MODE(ZXR10_MOT_TSEC_MACCFG2_IF_MODE_GMII_TBI))

/* CLRCNT = YES,  = NO,  STEN = YES,  TBIM = NO, RPM = NO, R100M = 10 */

#define ZXR10_MOT_TSEC_ECNTRL_DEFAULT  (ZXR10_MOT_TSEC_ECNTRL_STEN | ZXR10_MOT_TSEC_ECNTRL_AUTOZ)

#define ZXR10_MOT_TSEC_TBIPA_DEFAULT  (30)

#define ZXR10_MOT_TSEC_EDIS_DEFAULT (ZXR10_MOT_TSEC_EDIS_EBERRDIS 	| 	\
                               ZXR10_MOT_TSEC_EDIS_TXEDIS 	| 	\
			       ZXR10_MOT_TSEC_EDIS_LCDIS    	| 	\
                               ZXR10_MOT_TSEC_EDIS_CRLDIS 	| 	\
			       ZXR10_MOT_TSEC_EDIS_XFUNDIS )

/* Minimum Frame Receive Length */
#define ZXR10_MOT_TSEC_MINFLR_DEFAULT (64)
/* Tx Flow Control PAUSE Time Default  */
#define ZXR10_MOT_TSEC_PVT_DEFAULT  (ZXR10_MOT_TSEC_PTV_PTE(0)+ ZXR10_MOT_TSEC_PTV_PTE(0))

/* DMA Control Register Default */
#define ZXR10_MOT_TSEC_DMACTRL_DEFAULT  (ZXR10_MOT_TSEC_DMACTRL_TDSEN  | \
                                   ZXR10_MOT_TSEC_DMACTRL_TBDSEN | \
                                   ZXR10_MOT_TSEC_DMACTRL_WWR)

#define ZXR10_MOT_TSEC_FIFO_TX_THR_DEFAULT           (256)
#define ZXR10_MOT_TSEC_FIFO_TX_STARVE_DEFAULT        (128)
#define ZXR10_MOT_TSEC_FIFO_TX_STARVE_OFF_DEFAULT    (256)
/* Transmit Interrupt Coalescing */
#define ZXR10_MOT_TSEC_TXIC_DEFAULT ZXR10_MOT_TSEC_TXIC_ICFCT(18) | \
                              ZXR10_MOT_TSEC_TXIC_ICTT(0xffff)

/* BACK PRESSURE = NO, RFC_PAUSE = NO, TFC_PAUSE = NO */
#define ZXR10_MOT_TSEC_TCTRL_DEFAULT      (0)
#define ZXR10_MOT_TSEC_TSTAT_DEFAULT      (ZXR10_MOT_TSEC_TSTAT_THLT)

/* PROMISCUOUS = NO, BROAD_REJECT = NO, RX SHORT FRAMES = NO */
/*zhou modify ZXR10_MOT_TSEC_PROMISCUOUS_MODE|ZXR10_MOT_TSEC_RX_SHORT_FRAME*/
#define ZXR10_MOT_TSEC_RCTRL_DEFAULT      (0)
/*#define ZXR10_MOT_TSEC_RCTRL_DEFAULT      (ZXR10_MOT_TSEC_PROMISCUOUS_MODE|ZXR10_MOT_TSEC_RX_SHORT_FRAME)*/
#define ZXR10_MOT_TSEC_RSTAT_DEFAULT      (0)
#define ZXR10_MOT_TSEC_MRBLR_DEFAULT      ZXR10_MOT_TSEC_MRBLR(0x600)

#define ZXR10_MOT_TSEC_IPGIFG_DEFAULT     (ZXR10_MOT_TSEC_IPGIFG_NBBIPG1(0x40) | \
                                     ZXR10_MOT_TSEC_IPGIFG_NBBIPG2(0x60) | \
                                     ZXR10_MOT_TSEC_IPGIFG_MIFGE(0x50)   | \
                                     ZXR10_MOT_TSEC_IPGIFG_BBIPG(0x60))

#define ZXR10_MOT_TSEC_HAFDUP_DEFAULT     (ZXR10_MOT_TSEC_HALDUP_ALTBEB_TRUNC(0x0a) | \
                                     ZXR10_MOT_TSEC_HALDUP_RETRY(0x0f)        | \
                                     ZXR10_MOT_TSEC_HALDUP_COL_WINDOW(0x37)     )

#define ZXR10_MOT_TSEC_MAXFRM_DEFAULT      ZXR10_MOT_TSEC_MAXFRM(0x0600)
#define ZXR10_MOT_TSEC_MIICFG_DEFAULT     (ZXR10_MOT_TSEC_MIIMCFG_MCS(ZXR10_MOT_TSEC_MIIMCFG_MCS_14))
#define ZXR10_MOT_TSEC_MIICOM_DEFAULT      0
#define ZXR10_MOT_TSEC_IFSTAT_DEFAULT      0

#define ZXR10_MOT_TSEC_ATTR_DEFAULT  ((ZXR10_MOT_TSEC_ATTR_RDSEN)     | \
                                (ZXR10_MOT_TSEC_ATTR_BDLWT(ZXR10_MOT_TSEC_ATTR_BDLWT_L2)))

#define ZXR10_MOT_TSEC_ATTRELI_EL_DEFAULT (ZXR10_MOT_TSEC_ATTRELI_EL(0xc00) | \
                                     ZXR10_MOT_TSEC_ATTRELI_EI(0))



/*zhou add Eplogue protocol net buffer*/
#define BufferSize                0x1540

typedef struct
{
	UINT32 BufferIndex;
	UINT32 BufferAddr;
	UINT32 BufferLen;
} BufferList;

/* TSEC Register flags */
#define ZXR10_MOT_TSEC_FLAG_MINFLR      0x00000001
#define ZXR10_MOT_TSEC_FLAG_MAXFRM      0x00000002
#define ZXR10_MOT_TSEC_FLAG_PVT         0x00000004
#define ZXR10_MOT_TSEC_FLAG_TBIPA       0x00000008
#define ZXR10_MOT_TSEC_FLAG_FIFO_TX     0x00000010
#define ZXR10_MOT_TSEC_FLAG_IADDR       0x00000020
#define ZXR10_MOT_TSEC_FLAG_GADDR       0x00000040
#define ZXR10_MOT_TSEC_FLAG_MACCFG2     0x00000080
#define ZXR10_MOT_TSEC_FLAG_IPGIFGI     0x00000100
#define ZXR10_MOT_TSEC_FLAG_HAFDUP      0x00000200
#define ZXR10_MOT_TSEC_FLAG_MIICFG      0x00000400
#define ZXR10_MOT_TSEC_FLAG_ATTR        0x00000800

typedef struct
    {
    UINT32   phyAddr;        /* phy physical address */
    UINT32   phyDefMode;     /* default mode */
    UINT32   phyMaxDelay;    /* max delay */
    UINT32   phyDelayParm;   /* poll interval if in poll mode */
    MII_AN_ORDER_TBL * phyAnOrderTbl;  /* autonegotiation table */
    } ZXR10_MOT_TSEC_PHY_PARAMS;

typedef struct
    {
    VUINT16 bdStat;
    VUINT16 bdLen;
    VUINT32 bdAddr;
    } TSEC_BD;


typedef struct
    {
    UINT8   *memBufPtr;    /* Buffer pointer for allocated buffer space */
    UINT32   memBufSize;   /* Buffer pool size */
    TSEC_BD *bdBasePtr;    /* Descriptor Base Address */
    UINT32   bdSize;       /* Descriptor Size */
    UINT32   rbdNum;       /* Number of Receive Buffer Descriptors  */
    UINT32   tbdNum;       /* Number of Transmit Buffer Descriptors */
    } ZXR10_MOT_TSEC_PARAMS;

typedef struct
    {
    UINT32 usrBitFlags;     /* TSEC specific user bit flags */
    UINT32 usrRegFlags;     /* TSEC specific user reg flags */
    UINT32 minFrameLength;  /* Ethernet Minimum Frame Length */
    UINT32 maxFrameLength;  /* Ethernet Maximum Frame Length */

    /* TSEC Specific Device Parameters */
    UINT32 pauseTimeValue;  /* ext + pause time value */
    UINT32 tbiPhyAds;       /* Ten Bit Interface physical address */

    /* Tx FIFO Manipulation */
    UINT32 fifoTxTheshold;
    UINT32 fifoTxStarve;
    UINT32 fifoTxStarveShutOff;

    /* MAC specific Parameters */
    UINT32 macIndividualHash[8]; /* initial individual addresses [8]*/
    UINT32 macGroupHash[8];      /* initial group addresses [8]*/

    UINT32 macPreambleLength;
    UINT32 macIfMode;

    UINT32 macIpgifgNbbipg1;
    UINT32 macIpgifgNbbipg2;
    UINT32 macIpgifgMifge;
    UINT32 macIpgifgBbipg;

    /* MAC half duplex specific parameters */
    UINT32 macHalfDuplexAltBebTruncation;
    UINT32 macHalfDuplexRetryMaximum;
    UINT32 macHalfDuplexCollisionWindow;

    UINT32 miiMgmtClockSelect;
    UINT32 phyAddress;

    /* Misc */
    UINT32 extL2Cache;
    UINT32 bdL2Cache;
    UINT32 dmaExtLength;
    UINT32 dmaExtIndex;

    } ZXR10_MOT_TSEC_EXT_PARAMS;


/*-----------------------------------------------------------------*/
/*                   TSEC registers                                */
/*-----------------------------------------------------------------*/
typedef struct
    {
/* TSEC General Control and Status Registers */
    VUINT32 pad_1[4];
    VUINT32 ievent;
    VUINT32 imask;
    VUINT32 edis;
    VUINT32 pad_2;
    VUINT32 ecntrl;
    VUINT32 minflr;
    VUINT32 ptv;
    VUINT32 dmactrl;
    VUINT32 tbipa;
    VUINT32 pad_3[3];
    VUINT32 pad_4[19];

/* TSEC FIFO control and Status */
    VUINT32 fifoTxTheshold;
    VUINT32 pad_5[2];
    VUINT32 fifoTxStarve;
    VUINT32 fifoTxStarveShutoff;
    VUINT32 pad_6[24];

/* TSEC Transmit Control and Status Registers */
    VUINT32 tctrl;
    VUINT32 tstat;
    VUINT32 pad_7;
    VUINT32 tbdlen;
    VUINT32 txic;
    VUINT32 pad_8[4];
    VUINT32 ctbptr;
    VUINT32 pad_9[23];
    VUINT32 tbptr;
    VUINT32 pad_10[31];
    VUINT32 tbase;
    VUINT32 pad_11[42];
    VUINT32 ostbd;
    VUINT32 ostbdp;
    VUINT32 pad_12[18];

/* TSEC Receive Control and Status */
    VUINT32 rctrl;
    VUINT32 rstat;
    VUINT32 pad_13[1];
    VUINT32 rbdlen;
    VUINT32 pad_14[4];
    VUINT32 pad_15[1];
    VUINT32 crbptr;
    VUINT32 pad_16[6];
    VUINT32 mrblr;
    VUINT32 pad_17[16];
    VUINT32 rbptr;
    VUINT32 pad_18[31];
    VUINT32 rbase;
    VUINT32 pad_19[62];

/* TSEC MAC Registers */
    VUINT32 maccfg1;
    VUINT32 maccfg2;
    VUINT32 ipgifgi;
    VUINT32 hafdup;
    VUINT32 maxfrm;
    VUINT32 pad_20[1];
    VUINT32 pad_21[1];
    VUINT32 pad_22[1];

    VUINT32 miicfg;
    VUINT32 miicom;
    VUINT32 miimadd;
    VUINT32 miimcon;
    VUINT32 miimstat;
    VUINT32 miimind;
    VUINT32 pad_23[1];

    VUINT32 ifstat;
    VUINT32 macstnaddr1;
    VUINT32 macstnaddr2;
    VUINT32 pad_24[78];

/* TSEC Receive Counters */
    VUINT32 tr64;
    VUINT32 tr127;
    VUINT32 tr255;
    VUINT32 tr511;
    VUINT32 tr1k;
    VUINT32 trmax;
    VUINT32 trmgv;
    VUINT32 rbyt;
    VUINT32 rpkt;
    VUINT32 rfcs;
    VUINT32 rmca;
    VUINT32 rbca;
    VUINT32 rxcf;
    VUINT32 rxpf;
    VUINT32 rxuo;
    VUINT32 raln;
    VUINT32 rflr;
    VUINT32 rcde;
    VUINT32 rcse;
    VUINT32 rund;
    VUINT32 rovr;
    VUINT32 rfgr;
    VUINT32 rjbr;
    VUINT32 rdrp;

/* Transmit Counters */
    VUINT32 tbyt;
    VUINT32 tpkt;
    VUINT32 tmca;
    VUINT32 tbca;
    VUINT32 txpf;
    VUINT32 tdfr;
    VUINT32 tedf;
    VUINT32 tscl;
    VUINT32 tmcl;
    VUINT32 tlcl;
    VUINT32 txcl;
    VUINT32 tncl;
    VUINT32 pad_25[1];
    VUINT32 tdrp;
    VUINT32 tjbr;
    VUINT32 tfcs;
    VUINT32 tfcf;
    VUINT32 tovr;
    VUINT32 tund;
    VUINT32 tfrg;

 /* General Registers */
    VUINT32 car1;
    VUINT32 car2;
    VUINT32 cam1;
    VUINT32 cam2;
    VUINT32 pad_26[48];

/* Individual Hash function Registers */
    VUINT32 iaddr[8];
    VUINT32 pad_27[24];

/* Group Hash function Registers */
    VUINT32 gaddr[8];
    VUINT32 pad_28[214];

    VUINT32 attr;
    VUINT32 attreli;

/* TSEC Future Expansion Space */
    VUINT32 resv[256];
    } TSEC_REG_T;


typedef struct
    {
    UINT32  numInts;
    UINT32  numZcopySends;
    UINT32  numNonZcopySends;
    UINT32  numTXBInts;
    UINT32  numBSYInts;
    UINT32  numRXFInts;
    UINT32  numRXBInts;
    UINT32  numGRAInts;
    UINT32  numRXCInts;
    UINT32  numTXCInts;
    UINT32  numTXEInts;
    UINT32  nuzxr10_motHERInts;

    UINT32  numRXFHandlerEntries;
    UINT32  numRXFHandlerErrQuits;
    UINT32  numRXFHandlerFramesProcessed;
    UINT32  numRXFHandlerFramesRejected;
    UINT32  numRXFHandlerNetBufAllocErrors;
    UINT32  numRXFHandlerNetCblkAllocErrors;
    UINT32  numRXFHandlerNetMblkAllocErrors;
    UINT32  numRXFHandlerFramesCollisions;
    UINT32  numRXFHandlerFramesCrcErrors;
    UINT32  numRXFHandlerFramesLong;
    UINT32  numRXFExceedBurstLimit;

    UINT32  numNetJobAddErrors;

    UINT32  numRxStallsEntered;
    UINT32  numRxStallsCleared;

    UINT32  numTxStallsEntered;
    UINT32  numTxStallsCleared;
    UINT32  numTxStallErrors;

    UINT32  numLSCHandlerEntries;
    UINT32  numLSCHandlerExits;

    UINT32  txErr;
    UINT32  HbFailErr;
    UINT32  txLcErr;
    UINT32  txUrErr;
    UINT32  txCslErr;
    UINT32  txRlErr;
    UINT32  txDefErr;

    UINT32  rxBsyErr;
    UINT32  rxLgErr;
    UINT32  rxNoErr;
    UINT32  rxCrcErr;
    UINT32  rxOvErr;
    UINT32  rxShErr;
    UINT32  rxLcErr;
    UINT32  rxMemErr;
    } TSEC_DRIVER_STATS;


#define ZXR10_MOT_TSEC_FRAME_SET(p)        TSEC_REG_T * tsecReg = (p)->tsecRegsPtr;
#define ZXR10_MOT_TSEC_MII_FRAME_SET(p)    TSEC_REG_T * tsecMiiReg = (p)->tsecMiiPtr;