📄 geimiilib.h
字号:
/* technology ability field bit definitions */#define MII_TECH_10BASE_T 0x0020 /* 10Base-T */#define MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */#define MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */#define MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */#define MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */#define MII_TECH_PAUSE 0x0400 /* PAUSE */#define MII_TECH_ASM_PAUSE 0x0800 /* Asym pause */#define MII_TECH_PAUSE_MASK 0x0c00 #define MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */#define MII_TECH_MASK MII_ADS_TECH_MASK#define MII_ADS_SEL_MASK 0x001f /* selector field mask */#define MII_AN_FAIL 0x10 /* auto-negotiation fail */#define MII_STAT_FAIL 0x20 /* errors in the status register */#define MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities *//* MII management frame structure */#define MII_MF_PREAMBLE 0xffffffff /* preamble pattern */#define MII_MF_ST 0x1 /* start of frame pattern */#define MII_MF_OP_RD 0x2 /* read operation pattern */#define MII_MF_OP_WR 0x1 /* write operation pattern */#define MII_MF_PREAMBLE_LEN 0x20 /* preamble lenght in bit */#define MII_MF_ST_LEN 0x2 /* start frame lenght in bit */#define MII_MF_OP_LEN 0x2 /* op code lenght in bit */#define MII_MF_ADDR_LEN 0x5 /* PHY addr lenght in bit */#define MII_MF_REG_LEN 0x5 /* PHY reg lenght in bit */#define MII_MF_TA_LEN 0x2 /* turnaround lenght in bit */#define MII_MF_DATA_LEN 0x10 /* data lenght in bit *//* defines related to the PHY device */ #define MII_PHY_PRE_INIT 0x0001 /* PHY info pre-initialized */#define MII_PHY_AUTO 0x0010 /* auto-negotiation allowed */#define MII_PHY_TBL 0x0020 /* use negotiation table */#define MII_PHY_100 0x0040 /* PHY may use 100Mbit speed */#define MII_PHY_10 0x0080 /* PHY may use 10Mbit speed */#define MII_PHY_FD 0x0100 /* PHY may use full duplex */#define MII_PHY_HD 0x0200 /* PHY may use half duplex */#define MII_PHY_ISO 0x0400 /* isolate all PHYs */#define MII_PHY_PWR_DOWN 0x0800 /* power down mode */#define MII_PHY_DEF_SET 0x1000 /* set a default mode */#define MII_ALL_BUS_SCAN 0x2000 /* scan the all bus */#define MII_PHY_MONITOR 0x4000 /* monitor the PHY's status */#define MII_PHY_INIT 0x8000 /* PHY info initialized */#define MII_PHY_1000T_FD 0x10000 /* PHY may use 1000-T full duplex */#define MII_PHY_1000T_HD 0x20000 /* PHY mau use 1000-T half duplex */#define MII_PHY_TX_FLOW_CTRL 0x40000 /* Transmit flow control */#define MII_PHY_RX_FLOW_CTRL 0x80000 /* Receive flow control */#define MII_PHY_GMII_TYPE 0x100000 /* GMII = 1, MII = 0 *//* miscellaneous defines */#define MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */#define MII_PHY_NO_DELAY 0x0 /* do not delay */#define MII_PHY_NULL 0xff /* PHY is not present */#define MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */#ifndef MII_MONITOR_DELAY# define MII_MONITOR_DELAY 0x5 /* in seconds */#endif#define MII_PHY_LINK_UNKNOWN 0x0 /* link method - Unknown */#define MII_PHY_LINK_AUTO 0x1 /* link method - Auto-Negotiation */#define MII_PHY_LINK_FORCE 0x2 /* link method - Force link *//* * these values may be used in the default phy mode field of the load * string, since that is used to force the operating mode of the PHY * in case any attempt to establish the link failed. */ #define PHY_10BASE_T 0x00 /* 10 Base-T */#define PHY_10BASE_T_FDX 0x01 /* 10 Base Tx, full duplex */#define PHY_100BASE_TX 0x02 /* 100 Base Tx */#define PHY_100BASE_TX_FDX 0x03 /* 100 Base TX, full duplex */#define PHY_100BASE_T4 0x04 /* 100 Base T4 */#define PHY_AN_ENABLE 0x05 /* re-enable auto-negotiation */ #define MII_FDX_STR "full duplex" /* full duplex mode */#define MII_FDX_LEN sizeof (MII_FDX_STR) /* full duplex mode */#define MII_HDX_STR "half duplex" /* half duplex mode */#define MII_HDX_LEN sizeof (MII_HDX_STR) /* full duplex mode */#define MII_AN_TBL_MAX 20 /* max number of entries in the table *//* allowed PHY's speeds */#define MII_1000MBS 1000000000 /* bits per sec */ #define MII_100MBS 100000000 /* bits per sec */#define MII_10MBS 10000000 /* bits per sec *//* typedefs */typedef INT16 MII_AN_ORDER_TBL [MII_AN_TBL_MAX];typedef BOOL MII_PHY_BUS [MII_MAX_PHY_NUM];typedef struct mii_phy_node { NODE node; struct phy_info * pPhyInfo; } MII_PHY_NODE;/* * the structure below only represents the status of the PHY's registers * when they were last read through the MII interface */typedef struct mii_regs { UINT16 phyStatus; /* PHY's status register */ UINT16 phyCtrl; /* PHY's control register */ UINT16 phyId1; /* PHY's identifier field 1 */ UINT16 phyId2; /* PHY's identifier field 2 */ UINT16 phyAds; /* PHY's advertisement register */ UINT16 phyPrtn; /* PHY's partner register */ UINT16 phyExp; /* PHY's expansion register */ UINT16 phyNext; /* PHY's next page transmit register */ } MII_REGS;typedef struct mii_g_regs { UINT16 phyRcvNext; /* PHY'S partner received next page */ UINT16 phyMSCtrl; /* PHY'S MASTER-SLAVE Control register */ UINT16 phyMSStatus; /* PHY'S MASTER-SLAVE Status register */ UINT16 phyExtStatus; /* PHY'S extented Status register */ } MII_G_REGS;/* * the structure below is to be allocated and filled in by the * driver before it attempts to use the miiPhyInit () routine. Some * of its field may be overwritten by miiPhyInit (), since their initial * values may not be appropriate. In addition, some field do not have * to be initialized by the calling task, since miiPhyInit () may use a * default value, whereas some other are mandatory. To help understand this, * the comment for each field includes flags stating whether the relevent * field in the PHY_INFO structure is an input (I) parameter to miiPhyInit (), * an output (O) parameter, or an input-output (I/O) parameter first, * and then whether it is optional (O) or mandatory (M). For output * parameters, the second flag is a "don't care" (X). */typedef struct phy_info { MII_REGS miiRegs; /* PHY registers - (O|X) */ UINT8 phyAddr; /* address of a PHY - (I/O)|(O) */ UINT32 phyFlags; /* some flags - (I/O)|(O) */ UINT32 phySpeed; /* 10/100 Mbit/sec - (O|X) */ char phyMode[20]; /* half/full duplex mode - (O|X) */ UINT32 phyDefMode; /* default operating mode - (I|O) */ FUNCPTR phyReadRtn; /* phy read routine - (I|M) */ FUNCPTR phyWriteRtn; /* phy write routine - (I|M) */ FUNCPTR phyDelayRtn; /* phy delay routine - (I|O) */ UINT32 phyDelayParm; /* parameter to delay routine - (I|O) */ UINT32 phyMaxDelay; /* phy max delay - (I|O) */ void * pDrvCtrl; /* driver control structure - (I|M) */ MII_PHY_NODE * pMiiPhyNode; /* phy node - O */ MII_PHY_BUS * miiPhyPresent; /* which PHYs are there - O */ UINT32 phyLinkMethod; /* phy link method (Auto/Force) - (O|X) */ UINT32 phyAutoNegotiateFlags; /* flag for auto-negotiation - (O|X) */ MII_G_REGS miiGRegs; /* Giga Bit PHY registers - (O|X) */ FUNCPTR pPhyOptRegsRtn; /* device specific pPhyOptRegsRtn */ } PHY_INFO;/* globals */ void miiPhyOptFuncSet (FUNCPTR optRegsFunc);STATUS miiPhyInit (PHY_INFO * pPhyInfo);STATUS miiLibUnInit (void);STATUS miiLibInit (void);STATUS miiPhyUnInit (PHY_INFO * pPhyInfo);void miiShow (PHY_INFO * pPhyInfo);STATUS miiRegsGet (PHY_INFO * pPhyInfo, UINT regNum, UCHAR * buff);STATUS miiAnCheck (PHY_INFO * pPhyInfo, UINT8 phyAddr);#ifdef __cplusplus}#endif#endif /* __INCmiiLibh */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -