geimiilib.h

intel 82543 千兆网卡 vxworks驱动源码

/* miiLib.h - Media Independent Interface library header */

/* Copyright 1990-2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01i,13may02,rcs added pPhyOptRegsRtn field to PHY_INFO. SPR# 76711
01h,14jun01,rcs moved new registers used by GMII to new struc MII_G_REGS 
                and placed it at end of PHY_INFO. (SPR# 68502) 
01g,23feb01,jln add basic GMII support for 1000-T auto-negotiation (SPR# 68502)
01f,23nov99,cn  added miiLibInit () to make miiLib a component (SPR #29542).
01e,08nov99,cn  added fields phyLinkDownRtn, pMiiPhyNode, miiPhyPresent
		to PHY_INFO structure. New flags MII_ALL_BUS_SCAN,
		MII_PHY_MONITOR, and macro MII_MONITOR_DELAY. Also 
		added miiPhyUnInit (), miiLibUnInit ().
01d,27sep99,cn  added definition of MII_CR_DEF_0_MASK.
01c,13sep99,cn  added definition of MII_MAX_REG_NUM, moved global APIs
		from miiLib.c (SPR# 28305).
01b,15jun99,cn	changes after the code review.
01a,16mar99,cn	written from motFccEnd.h, 01b.
*/

/*
DESCRIPTION
 
This module implements a Media Independent Interface (MII) library.

INCLUDE FILES:
*/

#ifndef __INCmiiLibh
#define __INCmiiLibh

/* includes */

#ifdef __cplusplus
extern "C" {
#endif

#define S_miiLib_PHY_LINK_DOWN			(M_miiLib | 1)
#define S_miiLib_PHY_NULL		        (M_miiLib | 2)
#define S_miiLib_PHY_NO_ABLE             	(M_miiLib | 3)
#define S_miiLib_PHY_AN_FAIL             	(M_miiLib | 4)

/* defines */

#define MII_SYS_DELAY(delay)						\
if (pPhyInfo->phyDelayRtn != NULL)					\
    ((* (pPhyInfo->phyDelayRtn)) (delay))

#define MII_READ(addr, reg, val1, val2)					\
    val2 = ((* (pPhyInfo->phyReadRtn)) ((pPhyInfo->pDrvCtrl), 		\
					(addr), (reg), (val1)));

#define MII_WRITE(addr, reg, val1, val2)				\
    val2 = ((* (pPhyInfo->phyWriteRtn)) ((pPhyInfo->pDrvCtrl), 		\
					(addr), (reg), (val1)));

/* library flags */
 
#define MII_PHY_FLAGS_SET(setBits)                                      \
    (pPhyInfo->phyFlags |= (setBits))
 
#define MII_PHY_FLAGS_ARE_SET(setBits)                                  \
    (pPhyInfo->phyFlags & (setBits))
 
#define MII_PHY_FLAGS_GET(setBits)                                      \
    (pPhyInfo->phyFlags)
 
#define MII_PHY_FLAGS_CLEAR(clearBits)                                  \
    (pPhyInfo->phyFlags &= ~(clearBits))
 
/* MII definitions */

#define MII_CRC_LEN		0x4	/* CRC length in bytes */
#define MII_ETH_MAX_PCK_SZ      (ETHERMTU + SIZEOF_ETHERHEADER          \
				 + MII_CRC_LEN)
#define MII_MAX_PHY_NUM		0x20	/* max number of attached PHYs */
#define MII_MAX_REG_NUM         0x20    /* max number of registers */

#define MII_CTRL_REG		0x0	/* Control Register */
#define MII_STAT_REG		0x1	/* Status Register */
#define MII_PHY_ID1_REG		0x2	/* PHY identifier 1 Register */
#define MII_PHY_ID2_REG		0x3	/* PHY identifier 2 Register */
#define MII_AN_ADS_REG		0x4	/* Auto-Negotiation 	  */
					/* Advertisement Register */
#define MII_AN_PRTN_REG		0x5	/* Auto-Negotiation 	    */
					/* partner ability Register */
#define MII_AN_EXP_REG		0x6	/* Auto-Negotiation   */
					/* Expansion Register */
#define MII_AN_NEXT_REG		0x7	/* Auto-Negotiation 	       */
					/* next-page transmit Register */

#define MII_AN_PRTN_NEXT_REG	0x8  /* Link partner received next page */ 
#define MII_MASSLA_CTRL_REG	0x9  /* MATER-SLAVE control register */
#define MII_MASSLA_STAT_REG	0xa  /* MATER-SLAVE status register */
#define MII_EXT_STAT_REG	0xf  /* Extented status register */

/* MII control register bit  */

#define MII_CR_COLL_TEST	0x0080		/* collision test */
#define MII_CR_FDX		0x0100		/* FDX =1, half duplex =0 */
#define MII_CR_RESTART		0x0200		/* restart auto negotiation */
#define MII_CR_ISOLATE		0x0400		/* isolate PHY from MII */
#define MII_CR_POWER_DOWN	0x0800		/* power down */
#define MII_CR_AUTO_EN		0x1000		/* auto-negotiation enable */
#define MII_CR_100		0x2000		/* 0 = 10mb, 1 = 100mb */
#define MII_CR_LOOPBACK		0x4000		/* 0 = normal, 1 = loopback */
#define MII_CR_RESET		0x8000		/* 0 = normal, 1 = PHY reset */
#define MII_CR_NORM_EN		0x0000		/* just enable the PHY */
#define MII_CR_DEF_0_MASK       0xca7f          /* they must return zero */
#define MII_CR_RES_MASK       	0x003f          /* reserved bits,return zero */

/* MII Status register bit definitions */

#define MII_SR_LINK_STATUS	0x0004       	/* link Status -- 1 = link */
#define MII_SR_AUTO_SEL		0x0008       	/* auto speed select capable */
#define MII_SR_REMOTE_FAULT     0x0010      	/* Remote fault detect */
#define MII_SR_AUTO_NEG         0x0020      	/* auto negotiation complete */
#define MII_SR_10T_HALF_DPX     0x0800     	/* 10BaseT HD capable */
#define MII_SR_10T_FULL_DPX     0x1000    	/* 10BaseT FD capable */
#define MII_SR_TX_HALF_DPX      0x2000    	/* TX HD capable */
#define MII_SR_TX_FULL_DPX      0x4000     	/* TX FD capable */
#define MII_SR_T4               0x8000    	/* T4 capable */
#define MII_SR_ABIL_MASK        0xff80    	/* abilities mask */
#define MII_SR_EXT_CAP          0x0001    	/* extended capabilities */

/*  MII ID2 register bit mask */

#define MII_ID2_REVISON_MASK    0x000f
#define MII_ID2_MODE_MASK       0x03f0

/* MII AN advertisement Register bit definition */

#define MII_ANAR_10TX_HD        0x0020
#define MII_ANAR_10TX_FD        0x0040
#define MII_ANAR_100TX_HD       0x0080
#define MII_ANAR_100TX_FD       0x0100
#define MII_ANAR_100T_4         0x0200
#define MII_ANAR_PAUSE          0x0400
#define MII_ANAR_ASM_PAUSE      0x0800
#define MII_ANAR_REMORT_FAULT   0x2000
#define MII_ANAR_NEXT_PAGE      0x8000
#define MII_ANAR_PAUSE_MASK     0x0c00

/* MII Link Code word  bit definitions */

#define MII_BP_FAULT	0x2000       	/* remote fault */
#define MII_BP_ACK	0x4000       	/* acknowledge */
#define MII_BP_NP	0x8000       	/* nexp page is supported */

/* MII Next Page bit definitions */

#define MII_NP_TOGGLE	0x0800       	/* toggle bit */
#define MII_NP_ACK2	0x1000       	/* acknowledge two */
#define MII_NP_MSG	0x2000       	/* message page */
#define MII_NP_ACK1	0x4000       	/* acknowledge one */
#define MII_NP_NP	0x8000       	/* nexp page will follow */

/* MII Expansion Register bit definitions */

#define MII_EXP_FAULT	0x0010       	/* parallel detection fault */
#define MII_EXP_PRTN_NP	0x0008       	/* link partner next-page able */
#define MII_EXP_LOC_NP	0x0004       	/* local PHY next-page able */
#define MII_EXP_PR	0x0002       	/* full page received */
#define MII_EXP_PRT_AN	0x0001       	/* link partner auto negotiation able */

/* MII Master-Slave Control register bit definition */

#define MII_MASSLA_CTRL_1000T_HD    0x100
#define MII_MASSLA_CTRL_1000T_FD    0x200
#define MII_MASSLA_CTRL_PORT_TYPE   0x400
#define MII_MASSLA_CTRL_CONFIG_VAL  0x800
#define MII_MASSLA_CTRL_CONFIG_EN   0x1000

/* MII Master-Slave Status register bit definition */

#define MII_MASSLA_STAT_LP1000T_HD  0x400
#define MII_MASSLA_STAT_LP1000T_FD  0x800
#define MII_MASSLA_STAT_REMOTE_RCV  0x1000
#define MII_MASSLA_STAT_LOCAL_RCV   0x2000
#define MII_MASSLA_STAT_CONF_RES    0x4000
#define MII_MASSLA_STAT_CONF_FAULT  0x8000

/* MII Extented Status register bit definition */

#define MII_EXT_STAT_1000T_HD       0x1000
#define MII_EXT_STAT_1000T_FD       0x2000
#define MII_EXT_STAT_1000X_HD       0x4000
#define MII_EXT_STAT_1000X_FD       0x8000