gei82543end.h

intel 82543 千兆网卡 vxworks驱动源码

/* TX registers */

#define INTEL_82543GC_TDBAL             0x3800  /* Tx Descriptor Base Low */
#define INTEL_82543GC_TDBAH             0x3804  /* Tx Descriptor Base High */
#define INTEL_82543GC_TDLEN             0x3808  /* Tx Descriptor Length */
#define INTEL_82543GC_TDH               0x3810  /* Tx Descriptor Head */
#define INTEL_82543GC_TDT               0x3818  /* Tx Descriptor Tail */

/* RX registers */

#define INTEL_82543GC_RDBAL             0x2800  /* Rx Descriptor Base Low */
#define INTEL_82543GC_RDBAH             0x2804  /* Rx Descriptor Base High */
#define INTEL_82543GC_RDLEN             0x2808  /* Rx Descriptor Length */
#define INTEL_82543GC_RDH               0x2810  /* Rx Descriptor Head */
#define INTEL_82543GC_RDT               0x2818  /* Rx Descriptor Tail */

/* Interrupt registers */

#define INTEL_82543GC_ICR               0xc0    /* Interrupt Cause Read */
#define INTEL_82543GC_ICS               0xc8    /* Interrupt Cause Set */
#define INTEL_82543GC_IMS               0xd0    /* Interrupt Mask Set/Read */
#define INTEL_82543GC_IMC               0xD8    /* Interrupt Mask Clear */

#define INTEL_82543GC_CTRL              0x0     /* Device Control */
#define INTEL_82543GC_STATUS            0x8	/* Device Status */
#define INTEL_82543GC_EECD              0x10    /* EEPROM/Flash Data */
#define INTEL_82543GC_EERD              0x14    /* EEPROM Read Register*/

#define INTEL_82543GC_CTRL_EXT          0x18    /* Extended Device Control */
#define INTEL_82543GC_MDI               0x20    /* MDI Control */
#define INTEL_82543GC_FCAL              0x28    /* Flow Control Adr Low */
#define INTEL_82543GC_FCAH              0x2c    /* Flow Control Adr High */
#define INTEL_82543GC_FCT               0x30    /* Flow Control Type */
#define INTEL_82543GC_VET               0x38    /* VLAN EtherType */
#define INTEL_82546EB_ITR               0xc4    /* register for 82540/5/6 MAC only, 
                                                   interrupt throttle register */
#define INTEL_82543GC_RCTL              0x100   /* Receive Control */
#define INTEL_82543GC_FCTTV             0x170   /* Flow Ctrl TX Timer Value */
#define INTEL_82543GC_TXCW              0x178   /* TX Configuration Word */
#define INTEL_82543GC_RXCW              0x180   /* RX Configuration Word */
#define INTEL_82543GC_TCTL              0x400   /* TX control */
#define INTEL_82543GC_TIPG              0x410   /* Transmit IPG */
#define INTEL_82543GC_PBA               0x1000  /* Packet Buffer Allocation */
#define INTEL_82543GC_FCRTL             0x2160  /* Flow ctrl RX Threshold Lo*/
#define INTEL_82543GC_FCRTH             0x2168  /* Flow ctrl RX Threshold hi*/
#define INTEL_82543GC_RDTR              0x2820  /* Rx Delay Timer Ring */
#define INTEL_82546EB_RADV              0x282C  /* register for 82540/5/6 MAC only,
                                                   absolute Rx Delay Timer register */
#define INTEL_82543GC_TIDV              0x3820  /* Tx Interrupt Delay Value */
#define INTEL_82543GC_TXDCTL            0x3828  /* Transmit descriptor control */
#define INTEL_82546EB_TADV              0x382C  /* register for 82540/5/6 MAC only,
                                                   absolute Tx Interrupt Delay register */
#define INTEL_82543GC_RXCSUM            0x5000  /* Receive Checksum control */
#define INTEL_82543GC_MTA               0x5200  /* Multicast Table Array */
#define INTEL_82543GC_RAL               0x5400  /* Rx Adr Low */
#define INTEL_82543GC_RAH               0x5404  /* Rx Adr High */
#define INTEL_82543GC_VLAN              0x5600  /* VLAN Filter Table Array */

/* Statistic Registers */

#define INTEL_82543GC_CRCERRS           0x4000
#define INTEL_82543GC_ALGNERRC          0x4004
#define INTEL_82543GC_SYMERRS           0x4008
#define INTEL_82543GC_RXERRC            0x400c
#define INTEL_82543GC_MPC               0x4010
#define INTEL_82543GC_SCC               0x4014
#define INTEL_82543GC_ECOL              0x4018
#define INTEL_82543GC_MCC               0x401c
#define INTEL_82543GC_LATECOL           0x4020
#define INTEL_82543GC_COLC              0x4028
#define INTEL_82543GC_TUC               0x402c
#define INTEL_82543GC_DC                0x4030
#define INTEL_82543GC_TNCRS             0x4034
#define INTEL_82543GC_SEC               0x4038
#define INTEL_82543GC_CEXTEER           0x403c
#define INTEL_82543GC_RLEC              0x4040
#define INTEL_82543GC_XONRXC            0x4048
#define INTEL_82543GC_XONTXC            0x404c
#define INTEL_82543GC_XOFFRXC           0x4050
#define INTEL_82543GC_XOFFTXC           0x4054
#define INTEL_82543GC_FCRUC             0x4058
#define INTEL_82543GC_PRC64             0x405c
#define INTEL_82543GC_PRC127            0x4060
#define INTEL_82543GC_PRC255            0x4064
#define INTEL_82543GC_PRC511            0x4068
#define INTEL_82543GC_PRC1023           0x406c
#define INTEL_82543GC_PRC1522           0x4070
#define INTEL_82543GC_GPRC              0x4074
#define INTEL_82543GC_BPRC              0x4078
#define INTEL_82543GC_MPRC              0x407c
#define INTEL_82543GC_GPTC              0x4080
#define INTEL_82543GC_GORL              0x4088
#define INTEL_82543GC_GORH              0x408c
#define INTEL_82543GC_GOTL              0x4090
#define INTEL_82543GC_GOTH              0x4094
#define INTEL_82543GC_RNBC              0x40a0
#define INTEL_82543GC_RUC               0x40a4
#define INTEL_82543GC_RFC               0x40a8
#define INTEL_82543GC_ROC               0x40ac
#define INTEL_82543GC_RJC               0x40b0
#define INTEL_82543GC_TORL              0x40c0
#define INTEL_82543GC_TORH              0x40c4
#define INTEL_82543GC_TOTL              0x40c8
#define INTEL_82543GC_TOTH              0x40cc
#define INTEL_82543GC_TPR               0x40d0
#define INTEL_82543GC_TPT               0x40d4
#define INTEL_82543GC_PTC64             0x40d8
#define INTEL_82543GC_PTC127            0x40dc
#define INTEL_82543GC_PTC255            0x40e0
#define INTEL_82543GC_PTC511            0x40e4
#define INTEL_82543GC_PTC1023           0x40e8
#define INTEL_82543GC_PTC1522           0x40ec
#define INTEL_82543GC_MPTC              0x40f0
#define INTEL_82543GC_BPTC              0x40f4
#define INTEL_82543GC_TSCTC             0x40f8
#define INTEL_82543GC_TSCTFC            0x40fc
#define INTEL_82543GC_RDFH              0x2410
#define INTEL_82543GC_RDFT              0x2418
#define INTEL_82543GC_RDFHS             0x2420
#define INTEL_82543GC_RDFTS             0x2428
#define INTEL_82543GC_RDFPC             0x2430
#define INTEL_82543GC_TDFH              0x3410
#define INTEL_82543GC_TDFT              0x3418
#define INTEL_82543GC_TDFHS             0x3420
#define INTEL_82543GC_TDFTS             0x3428
#define INTEL_82543GC_TDFPC             0x3430
#define INTEL_82543GC_RX_PBM            0x10000
#define INTEL_82543GC_TX_PBM            0x1c000
/* Rx Configuration Word Field */

#define RXCW_C_BIT                      0x20000000

/* EEPROM Structure */

#define EEPROM_WORD_SIZE                0x40      /* 0-0x3f */
#define EEPROM_SUM                      0xBABA
#define EEPROM_INDEX_SIZE               0x40
#define EEPROM_INDEX_BITS               6
#define EEPROM_CMD_BITS                 3
#define EEPROM_DATA_BITS                16
#define EEPROM_READ_OPCODE              0x6
#define EEPROM_WRITE_OPCODE             0x5
#define EEPROM_ERASE_OPCODE             0x7

#define EEPROM_IA_ADDRESS               0x0
#define EEPROM_ICW1                     0xa
#define EEPROM_ICW1_SWDPIO_BITS         0x1e0
#define EEPROM_ICW1_SWDPIO_SHIFT        5
#define EEPROM_ICW1_ILOS_BIT            0x10
#define EEPROM_ICW1_FRCSPD_BIT          0x800
#define EEPROM_ICW1_ILOS_SHIFT          4

#define EEPROM_ICW2                     0xf
#define EEPROM_ICW2_PAUSE_BITS          0x3000
#define EEPROM_ICW2_ASM_DIR             0x2000
#define EEPROM_ICW2_SWDPIO_EXE_BITS     0xf0
#define EEPROM_ICW2_SWDPIO_EXE_SHIFT    4

#define BAR0_64_BIT                     0x04

/* TX Descriptor Command Fields */

#define TXD_CMD_EOP                     0x01
#define TXD_CMD_IFCS                    0x02
#define TXD_CMD_IC                      0x04
#define TXD_CMD_RS                      0x08
#define TXD_CMD_RPS                     0x10
#define TXD_CMD_DEXT                    0x20
#define TXD_CMD_VLE                     0x40
#define TXD_CMD_IDE                     0x80

/* for TX context descriptor only

#define TXD_CMD_CTX_TCP                 0x01     1 == TCP, 0 == UDP 
#define TXD_CMD_CTX_IP			0x02
#define TXD_CMD_CTX_TSE			0x04
#define TXD_CMD_CTX_RS			0x08
#define TXD_CMD_CTX_DEXT		0x20
#define TXD_CMD_CTX_IDE			0x80 */

/* TX Descriptor Status Fields */

#define TXD_STAT_DD                     0x01
#define TXD_STAT_EC                     0x02
#define TXD_STAT_LC                     0x04
#define TXD_STAT_TU                     0x08

/* TX Data Descriptor POPTS fields */

#define TXD_DATA_POPTS_IXSM_BIT         0x01
#define TXD_DATA_POPTS_TXSM_BIT         0x02

/* TX Data Descriptor DTYP Fileld */ 
#define TXD_DTYP_BIT                    0x01

/* RX Descriptor Status Field */

#define RXD_STAT_DD                     0x01
#define RXD_STAT_EOP                    0x02
#define RXD_STAT_IXSM                   0x04
#define RXD_STAT_VP                     0x08
#define RXD_STAT_RSV                    0x10
#define RXD_STAT_TCPCS                  0x20
#define RXD_STAT_IPCS                   0x40
#define RXD_STAT_PIF                    0x80

/* RX Descriptor Error Field */

#define RXD_ERROR_CE                    0x01        /* CRC or Align error */
#define RXD_ERROR_SE                    0x02        /* Symbol error */
#define RXD_ERROR_SEQ                   0x04        /* Sequence error */
#define RXD_ERROR_RSV                   0x08        /* reserved */
#define RXD_ERROR_CXE                   0x10        /* Carrier ext error */
#define RXD_ERROR_TCPE                  0x20        /* TCP/UDP CKSUM error */
#define RXD_ERROR_IPE                   0x40        /* IP CKSUM error */
#define RXD_ERROR_RXE                   0x80        /* RX data error */

/* Interrupt Register Fields */

#define INT_TXDW_BIT                    0x01        /* TX descriptor write-back */        
#define INT_TXQE_BIT                    0x02        /* TX ring empty */
#define INT_LSC_BIT                     0x04        /* link change interrupt */
#define INT_RXSEQ_BIT                   0x08        /* RX sequence error */
#define INT_RXDMT0_BIT                  0x10        /* RX descriptor Mini Threshold */
#define INT_RXO_BIT                     0x40        /* RX FIFO overrun */
#define INT_RXTO_BIT                    0x80        /* RX timer interrupt */
#define INT_MDAC_BIT                    0x200       /* MDIO complete interrupt */
#define INT_RXCFG_BIT                   0x400       /* Receiving /C/ ordered set */
#define INT_GPI0_BIT                    0x800       /* GPIO 0 interrupt (543 MAC) */
#define INT_GPI1_BIT                    0x1000      /* PHY (544 MAC) or GPIO1 (543) interrupt */ 
#define INT_GPI2_BIT                    0x2000      /* GPIO2 interrupt */
#define INT_GPI3_BIT                    0x4000      /* GPIO3 interrupt */
#define INT_TXDLOW_BIT                  0x8000      /* TX descriptor low threshold hit */

/* IMS register */ 

#define IMS_TXDW_BIT                    0x01
#define IMS_TXQE_BIT                    0x02
#define IMS_LSC_BIT                     0x04
#define IMS_RXSEQ_BIT                   0x08
#define IMS_RXDMT0_BIT                  0x10
#define IMS_RXO_BIT                     0x40
#define IMS_RXTO_BIT                    0x80
#define IMS_MDAC_BIT                    0x200
#define IMS_RXCFG_BIT                   0x400
#define IMS_TXDLOW_BIT                  0x8000

/* IMC register */

#define IMC_ALL_BITS                    0xffffffff
#define IMC_TXDW_BIT                    0x01
#define IMC_TXQE_BIT                    0x02
#define IMC_LSC_BIT                     0x04
#define IMC_RXSEQ_BIT                   0x08
#define IMC_RXDMT0_BIT                  0x10
#define IMC_RXO_BIT                     0x40
#define IMC_RXTO_BIT                    0x80
#define IMC_MDAC_BIT                    0x200
#define IMC_RXCFG_BIT                   0x400
#define IMC_TXDLOW_BIT                  0x8000

/* ICR register */

#define ICR_TXDW_BIT                    0x01
#define ICR_TXQE_BIT                    0x02
#define ICR_LSC_BIT                     0x04
#define ICR_RXSEQ_BIT                   0x08
#define ICR_RXDMT0_BIT                  0x10
#define ICR_RXO_BIT                     0x40
#define ICR_RXTO_BIT                    0x80
#define ICR_MDAC_BIT                    0x200
#define ICR_RXCFG_BIT                   0x400
#define ICR_TXDLOW_BIT                  0x8000

/* EEPROM Register Fields */

#define EECD_SK_BIT                     0x1
#define EECD_CS_BIT                     0x2
#define EECD_DI_BIT                     0x4
#define EECD_DO_BIT                     0x8
#define EECD_REQ_BIT                    0x40
#define EECD_GNT_BIT                    0x80
#define EECD_PRES_BIT                   0x100
#define EECD_SIZE_BIT                   0x200

#define EERD_START_BIT                  0x1
#define EERD_DONE_BIT                   0x10
#define EERD_ADDR_SHIFT                 8
#define EERD_DATA_SHIFT                 16