sec2driver.h

freescale ppc sec2加解密单元驱动

/* All possible channel done interrupts from high interrupt status word */
#define ALL_CHANNEL_INT_DONE_MASK ((unsigned long)0x00000055)
#define CHANNEL_INT_DONE_1        ((unsigned long)0x00000001)
#define CHANNEL_INT_DONE_2        ((unsigned long)0x00000004)
#define CHANNEL_INT_DONE_3        ((unsigned long)0x00000010)
#define CHANNEL_INT_DONE_4        ((unsigned long)0x00000040)

/* All possible CHA done interrupts from low interrupt status word */
#define ALL_CHA_INT_DONE_MASK ((unsigned long)0x00111111)
#define CHA_INT_DONE_DEU      ((unsigned long)0x00000001)
#define CHA_INT_DONE_AESU     ((unsigned long)0x00000010)
#define CHA_INT_DONE_MDEU     ((unsigned long)0x00000100)
#define CHA_INT_DONE_AFEU     ((unsigned long)0x00001000)
#define CHA_INT_DONE_RNG      ((unsigned long)0x00010000)
#define CHA_INT_DONE_PKEU     ((unsigned long)0x00100000)

/* All possible channel error interrupts from high interrupt status word */
#define ALL_CHANNEL_INT_ERROR_MASK ((unsigned long)0x000000aa)
#define CHANNEL_INT_ERROR_1        ((unsigned long)0x00000002)
#define CHANNEL_INT_ERROR_2        ((unsigned long)0x00000008)
#define CHANNEL_INT_ERROR_3        ((unsigned long)0x00000020)
#define CHANNEL_INT_ERROR_4        ((unsigned long)0x00000080)

/* All possible CHA done interrupts from low interrupt status word */
#define ALL_CHA_INT_ERROR_MASK     ((unsigned long)0x00222222)
#define ALL_CHA_INT_DONE_MASK      ((unsigned long)0x00111111)
#define CHA_INT_ERROR_DEU      ((unsigned long)0x00000002)
#define CHA_INT_ERROR_AESU     ((unsigned long)0x00000020)
#define CHA_INT_ERROR_MDEU     ((unsigned long)0x00000200)
#define CHA_INT_ERROR_AFEU     ((unsigned long)0x00002000)
#define CHA_INT_ERROR_RNG      ((unsigned long)0x00020000)
#define CHA_INT_ERROR_PKEU     ((unsigned long)0x00200000)

/*ERROR done interrupts*/
#define DONE_OVERFLOW          ((unsigned long)0x00000f00)
#define INTERNAL_TIME_OUT      ((unsigned long)0x00010000)

/*! \struct device_regs
    \brief A grouping of status and error indication registers
*/
typedef struct device_regs
{
    unsigned long IntStatus[2];                     /*!< The Interrupt
                                                    Status Register
                                                    (#sec2_InterruptStatusRegister)*/
    unsigned long IntStatusDbg[2];                  /*!< The Interrupt
                                                    Status Register
                                                    (#sec2_InterruptStatusRegister)*/
    unsigned long ChaAssignmentStatus[2];           /*!< The CHA
                                                    Assignment Status
                                                    Register
                                                    (#sec2_ChaAssignmentStatusRegister)
                                                    */
    unsigned long ChannelError[SEC2_NUM_CHANNELS][2];    /*!< An array of
                                                    Channel Pointer Status
                                                    Registers.  One per
                                                    channel
                                                    (#sec2_ChannelPointerStatusRegister)
                                                    */
    unsigned long ChaError[NUM_CHAS][2];            /*!< an array of
                                                    CHA Interrupt Status
                                                    Registers.  One per CHA
                                                    (#Sec2ChaInterruptStatusRegister)
                                                    */
}SEC2_DEVICE_REGS;



/* Queueing */
#ifdef __KERNEL__
#define PREGS_QUEUE_DEPTH 16
extern DEVICE_REGS SEC2_DEVICE_REGS[PREGS_QUEUE_DEPTH];
extern unsigned PQ_head, PQ_tail, PQ_entries;

#define QmsgSend() \
        if (PQ_entries == PREGS_QUEUE_DEPTH) { \
                panic("SEC driver's pRegs queue overflow!"); \
        } \
        pRegs_queue[PQ_tail] = *pRegs; \
        PQ_tail = (PQ_tail + 1) % PREGS_QUEUE_DEPTH; \
        PQ_entries ++; \
        tasklet_schedule(&isr_tasklet)

#define QmsgWait() \
        disable_irq(MPC85xx_IRQ_SEC); \
        if (!PQ_entries) { \
                enable_irq(MPC85xx_IRQ_SEC); break;} \
        *pRegs = pRegs_queue[PQ_head]; \
        PQ_head = (PQ_head + 1) % PREGS_QUEUE_DEPTH; \
        PQ_entries --; \
        enable_irq(MPC85xx_IRQ_SEC)
#endif




/* Components of a SEC2 scatter/gather list element. This is the native format */
/* that the channel processor expects to see so as to translate a scattered    */
/* buffer in the course of processing                                          */


#define MAX_SCATTER_FRAGS 1024  /* limit of static fragment descriptor pool */

/* used in "linkStat" below */
#define SEGLIST_RETURN 0x0200
#define SEGLIST_NEXT   0x0100

typedef struct _sec2scatterListElement
{
  unsigned short segLen;
  unsigned short linkStat;
  void          *segAddr;
} SCATTER_ELEMENT;


#if 0
#if defined(SEC2_GLOBAL) || defined(__cplusplus)

/*  unsigned long Sec2ChaDoneInterruptMasks[NUM_CHAS]
    An array of CHA done completion bit masks.

    The index of the array represents the CHA.  This bit mask
    is applied against #sec2_InterruptStatusRegister in order to
    determine if an interrupt is due to a CHA completion or not.
    六个CHA*/
const unsigned long Sec2ChaDoneInterruptMasks[NUM_CHAS] = 
{
    0x00000001,
    0x00000010,
    0x00000100,
    0x00001000,
    0x00010000,
    0x00100000

};

/*  unsigned long ChannelDoneInterruptMasks[SEC2_NUM_CHANNELS]
    An array of channel done completion bit masks.

    The index of the array represents the channel.  This bit mask
    is applied against #sec2_InterruptStatusRegister in order to
    determine if an interrupt is due to a channel completion or not.
*/
const unsigned long Sec2ChannelDoneInterruptMasks[SEC2_NUM_CHANNELS] = 
{
    0x00000001,
    0x00000004,
    0x00000010,
    0x00000040
};

/*! \var unsigned long Sec2ChannelErrorInterruptMasks[SEC2_NUM_CHANNELS]
    \brief An array of channel error bit masks.

    The index of the array represents the channel.  This bit mask
    is applied against #sec2_InterruptStatusRegister in order to
    determine if an interrupt is due to a channel error or not.
*/
const unsigned long Sec2ChannelErrorInterruptMasks[SEC2_NUM_CHANNELS] = 
{
    0x00000002,
    0x00000008,
    0x00000020,
    0x00000080
};

/*! \var unsigned long Sec2ChaErrorInterruptMasks[NUM_CHAS]
    \brief An array of CHA error bit masks.

    The index of the array represents the CHA.  This bit mask
    is applied against #sec2_InterruptStatusRegister in order to
    determine if an interrupt is due to a CHA error or not.
*/
const unsigned long Sec2ChaErrorInterruptMasks[NUM_CHAS] =
{
    0x00000002,
    0x00000020,
    0x00000200,
    0x00002000,
    0x00020000,
    0x00200000
};

#else

extern const unsigned long Sec2ChaDoneInterruptMasks[];
extern const unsigned long Sec2ChannelDoneInterruptMasks[];
extern const unsigned long Sec2ChannelErrorInterruptMasks[];
extern const unsigned long Sec2ChaErrorInterruptMasks[];

#endif
#endif

/*  SEC2_GLOBAL
    A definition used to control allocation and referencing
    of global variables.
    
    When the definition is not set it is considered
    to be used as a reference (extern is prepended).

    When the definition is set (to nothing) it is considered to be
    allocating the global variable.  This is done in one place
    only.  In init.c
*/

/*  SEC2_CHANNEL_ASSIGNMENT ChannelAssignments
    A global variable which is a array of channel assignment
    structures.  Each channel is reqresented by its own channel
    assignment structure.
*/
#ifndef SEC2_GLOBAL
#define SEC2_GLOBAL  extern
#endif

SEC2_GLOBAL SEC2_DPD sec2_Descriptors[SEC2_NUM_CHANNELS][MAX_DPDS] ;
SEC2_GLOBAL SEC2_CHANNEL_ASSIGNMENT Sec2_ChannelAssignments[SEC2_NUM_CHANNELS];
SEC2_GLOBAL SEC2_DPD *Sec2_dpd[SEC2_NUM_CHANNELS][MAX_DPDS];
SEC2_GLOBAL QUEUE_ENTRY sec2_Queue[SEC2_HANDLE_QUEUE_DEPTH];
SEC2_GLOBAL SEC2_FWD_QUEUE *gpSec2_fwd_Queue ;
SEC2_GLOBAL DRV_SEC2_END *gpDrvSec2End;

/*  A global variable which is an array of CHAs that
    are assigned to channels.
        
    The value in each element is either
    #CHA_BUSY which is unassigned or the channel that is
    assigned (1-4) to the CHA represented by the array index.
*/
SEC2_GLOBAL unsigned char sec2_ChaAssignments[16];

/*  A global variable which is the address of the base
    address register for the SEC2 coprocessor
    
    All registers accessed are offsets from this register.
    This variable is initialized during startup.
*/

SEC2_GLOBAL unsigned long sec2_IOBaseAddress;

/*  A global variable which is a pointer to the CHA
    Assignment Status Register
    
    This variable is initialized during startup.  It is determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChaAssignmentStatusRegister;

/*  A global variable which is a pointer to the CHA
    Assignment Control Register
    
    This variable is initialized during startup.  It is determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChaAssignmentControlRegister;

/*  A global variable which is a pointer to the Interrupt
    Control Register
    
    This variable is initialized during startup.  It is determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_InterruptControlRegister;

/*  A global variable which is a pointer to the Interrupt
    Status Register
    
    This variable is initialized during startup.  It is determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_InterruptStatusRegister;

/*  A global variable which is a pointer to the Interrupt
    Clear Register
    
    This variable is initialized during startup.  It is determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_InterruptClearRegister;

/*  A global variable which is a pointer to the ID Register
    
    This variable is initialized during startup.  It is determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_IdRegister;

/*  A global variable which is a array of pointers to the
    Channel Config Registers.  There is one per channel.
    
    This pointers are initialized during startup.  They are determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChannelConfigRegister[SEC2_NUM_CHANNELS];

/*  A global variable which is a array of pointers to the
    Channel Pointer Status Registers.  There is one per channel.
    
    This pointers are initialized during startup.  They are determined
    to be a fixed offset from the #IOBaseAddress

    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChannelPointerStatusRegister[SEC2_NUM_CHANNELS];

/*  A global variable which is a array of pointers to the
    Channel Next Descriptor Registers.  There is one per channel.
    
    This pointers are initialized during startup.  They are determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChannelNextDescriptorRegister[SEC2_NUM_CHANNELS];

/*  A global variable which is a array of pointers to the
    CHA Reset Control Registers.  There is one per CHA.
    
    This pointers are initialized during startup.  They are determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChaResetControlRegister[NUM_CHAS];

/*  A global variable which is a array of pointers to the
    CHA Interrupt Status Registers.  There is one per CHA.
    
    This pointers are initialized during startup.  They are determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *Sec2ChaInterruptStatusRegister[NUM_CHAS];

/*  A global variable which is a array of pointers to the
    CHA Interrupt Control Registers.  There is one per CHA.
    
    This pointers are initialized during startup.  They are determined
    to be a fixed offset from the #IOBaseAddress
    register.  See the SEC2 manual for details.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChaInterruptControlRegister[NUM_CHAS];

/*  Debugging Only variables.
*/
SEC2_GLOBAL volatile unsigned long *sec2_ChannelDataBufferDescriptorRegister[SEC2_NUM_CHANNELS];
SEC2_GLOBAL volatile unsigned long *sec2_ChannelDataBufferDescriptorRegister[SEC2_NUM_CHANNELS];

/*  long *sec2_MasterControlRegister
    A global variable which is a pointer to the
    Master Control Register