sec2driver.h

freescale ppc sec2加解密单元驱动

/* Least-significant 4 bits may end up as sub-version mask */
#define SEC_COREID_2_0_0 (0x00000040)
#define SEC_COREID_2_0_1 (0x00000041)
#define SEC_COREID_2_1_0 (0x00000080)


/*! \def CHA_ASSIGNMENT_STATUS_OFFSET
    \brief Offset for the CHA Assignment Control Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_ChaAssignmentStatusRegister variable during Driver Startup
*/
#define CHA_ASSIGNMENT_STATUS_OFFSET ((unsigned long)0x00001028)

/*! \def CHANNEL_CONFIG_BASE
    \brief Base address for the Channel # 1's
    Channel Configuration Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_ChannelConfigRegister variable array during Driver Startup
    Each channel has a Channel Configuration Register that is offset
    #CHANNEL_DISTANCE from the previous.
*/
#define CHANNEL_CONFIG_BASE ((unsigned long)0x00001108)


/*! \def CHANNEL_POINTER_STATUS_BASE
    \brief Base address for the Channel # 1's
    Channel Pointer Status Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #ChannelPointerStatusRegister variable array during Driver Startup
    Each channel has a Channel Pointer Status Register that is offset
    #CHANNEL_DISTANCE from the previous.
*/
#define CHANNEL_POINTER_STATUS_BASE ((unsigned long)0x00001110)

/*! \def CHANNEL_NEXT_DESCRIPTOR_BASE
    \brief Base address for the Channel # 1's
    Channel Next Descriptor Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_ChannelNextDescriptorRegister variable array during Driver Startup
    Each channel has a Channel Next Descriptor Register that is offset
    #CHANNEL_DISTANCE from the previous.
*/
#define CHANNEL_NEXT_DESCRIPTOR_BASE ((unsigned long)0x00001148)

/*  Debugging Only definition
*/

#define CHANNEL_DBR_BASE ((unsigned long)0x00001180)
#define CHANNEL_CDPR_BASE ((unsigned long)0x00002040)

/*! \def CHANNEL_DISTANCE
    \brief Number of bytes to the next channel register
*/
#define CHANNEL_DISTANCE ((unsigned long)0x00000100)

/*! \def CHA_RESET_CONTROL_BASE
    \brief Base address for the CHA # 1 (DES)
    CHA Reset Control Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_ChaResetControlRegister variable array during Driver Startup
    Each CHA has a CHA Reset Control Register that is offset
    #CHA_DISTANCE from the previous.
*/
#define CHA_RESET_CONTROL_BASE ((unsigned long)0x00002018)

/*! \def CHA_INTERRUPT_STATUS_BASE
    \brief Base address for the CHA # 1 (DES)
    CHA Interrupt Status Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #Sec2ChaInterruptStatusRegister variable array during Driver Startup
    Each CHA has a CHA Interrupt Status Register that is offset
    #CHA_DISTANCE from the previous.
*/
#define CHA_INTERRUPT_STATUS_BASE ((unsigned long)0x00002030)

/*! \def CHA_INTERRUPT_CONTROL_BASE
    \brief Base address for the CHA # 1 (DES)
    CHA Interrupt Control Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_ChaInterruptControlRegister variable array during Driver Startup
    Each CHA has a CHA Interrupt Control Register that is offset
    #CHA_DISTANCE from the previous.
*/
#define CHA_INTERRUPT_CONTROL_BASE ((unsigned long)0x00002038)

/*! \def AFHA_STATUS_OFFSET
    \brief Debugging Only definition.
*/
#define AFHA_STATUS_OFFSET ((unsigned long)0x0008028)

/*! \def PKHA_STATUS_BASE
    \brief Debugging Only definition.
*/
#define PKHA_STATUS_BASE ((unsigned long)0x0000C028)


/*  CHA_DISTANCE
    Number of bytes to the next CHA register
*/
#define CHA_DISTANCE ((unsigned long)0x00002000)


/*  CHANNEL_INTEN
    Channel Interrupt Enable
*/
#define CHANNEL_INTEN ((unsigned long)0x00000002)
#define CHANNEL_GOLOBAL_INT_EN ((unsigned long)0x00000004)
/* Force channel burst size to 128 bytes (normal default is 64) */
#define CHANNEL_BURST128 ((unsigned long)0x00000100)



/*  CHANNEL_RESET
    Bit field setting to write to the 
    #sec2_ChannelConfigRegister in order to reset the channel. First Word

    The bit setting indicates that we are resetting the channel
*/
#define CHANNEL_RESET ((unsigned long)0x00000001)



/*  Bit field mask for reading from the
    #ChannelPointerStatusRegister in order
    to determine if a CHA assigned to the channel generated
    an error or not. First Word
*/
#define CHANNEL_CHA_ERROR_DOF ((unsigned long)0x80000000)

#define CHANNEL_CHA_ERROR_SOF ((unsigned long)0x40000000)

#define CHANNEL_CHA_ERROR_GER ((unsigned long)0x00100000)

#define CHANNEL_CHA_ERROR_SES ((unsigned long)0x00001000)

/*  Bit field mask for reading from the
    #ChannelPointerStatusRegister in order
    to determine if there is an illegal descriptor or not
    Second Word
*/

#define CHANNEL_SCATTER_LENGTH_ERROR      ((unsigned long) 0x00000010)
#define CHANNEL_SCATTER_BOUND_ERROR       ((unsigned long) 0x00000020)
#define CHANNEL_GATHER_LENGTH_ERROR       ((unsigned long) 0x00000040)
#define CHANNEL_GATHER_BOUND_ERROR        ((unsigned long) 0x00000080)
#define CHANNEL_CHA_ERROR                 ((unsigned long) 0x00000100)
#define CHANNEL_CHA_ASSIGN_ERROR          ((unsigned long) 0x00000200)
#define CHANNEL_UNRECOGNIZED_HEADER_ERROR ((unsigned long) 0x00000400)
#define CHA_PARITY_SYSTEM_ERROR           ((unsigned long) 0x00000800) /* compatibility */
#define CHANNEL_NULL_FETCH_POINTER        ((unsigned long) 0x00000800)
#define CHANNEL_ZERO_SCATTER_LEN_ERROR    ((unsigned long) 0x00001000)
#define CHANNEL_BUS_MASTER_ERROR          ((unsigned long) 0x00002000)
#define CHANNEL_FETCH_FIFO_NEARMISS_ERROR ((unsigned long) 0x00004000)
#define CHANNEL_FETCH_FIFO_OVERFLOW_ERROR ((unsigned long) 0x00008000)

/*! \def SET_ALL_CHA_INT_DONE_MASK
    \brief Bit field setting to write to the 
    #sec2_InterruptControlRegister in order to disable interrupts when
    any of the CHAs have completed an operation
*/
/*! \def SET_ALL_CHA_INT_DONE_MASK
    \brief Bit field setting to write to the 
    #sec2_InterruptControlRegister in order to disable interrupts when
    any of the CHAs have completed an operation
*/
/*! \def CHA_SOFTWARE_RESET
    \brief Bit field setting to write to any of the 
    #sec2_ChaResetControlRegister"s" in order to software reset the CHA
*/
/*! \def CHA_MODULE_INIT
    \brief Bit field setting to write to any of the 
    #sec2_ChaResetControlRegister"s" in order to initialize the CHA
*/
/*! \def CHA_RESET_INT
    \brief Bit field setting to write to any of the 
    #sec2_ChaResetControlRegister"s" in order to reset the CHA
*/
/*! \def CHA_RESET_INT
    \brief Bit field setting to write to any of the 
    #sec2_ChaResetControlRegister"s" in order to reset the CHA
*/
/*! \def CHA_DESA_KEY_PARITY_ERROR_DISABLE
    \brief Bit field setting to write to any of the
    #sec2_ChaInterruptControlRegister"s" in order to disable parity errors
    for the CHA.  This is only good for DES specific CHAs.
*/
/*! \def CHA_PKHA_ILLEGAL_ADDR_ERROR_DISABLE
    \brief Bit field setting to write to any of the
    #sec2_ChaInterruptControlRegister"s" in order to disable illegal address errors
    for the CHA.  This is only good for PK specific CHAs.
*/
#define SET_ALL_CHA_INT_DONE_MASK ((unsigned long)0x00111111)
#define CHA_SOFTWARE_RESET ((unsigned long)0x00000001)
#define CHA_DESA_KEY_PARITY_ERROR_DISABLE ((unsigned long)0x00002000)
#define CHA_PKHA_ILLEGAL_ADDR_ERROR_DISABLE ((unsigned long)0x00000040)


/*  This is the physical representation of a DPD.  It is how
    the SEC2 sees a DPD.
*/
typedef struct SEC2_dpd
{
    unsigned long header;
    unsigned long dpd_reserved;
/*  Each field in a DPD.  They are length and pointer pairs. */
    struct dpd_fld
    {
        unsigned long len;
        unsigned long ptr;
    } fld[NUM_DPD_FLDS];
}SEC2_DPD;

/*  SEC2_CHANNEL_ASSIGNMENT Controls the assignment of channels  */
typedef struct sec2_channel_assignment
{
    unsigned char       assignment;     /* The current state of the channel.
                                        It can be one of the following values:
                                        #CHANNEL_FREE, or #CHANNEL_BUSY
                                        */
    int                 ownerTaskId;    /* Task Id that currently owns the
                                        channel.
                                        */
    GENERIC_REQ         *pReq;          /* Pointer to the start of a linked
                                        list describing the request
                                        */
    DPD_DETAILS_ENTRY   *pDesc;
    
    GENERIC_REQ         *pCurrReq;      /* Pointer to the current linked list
                                        member.  Used when the list is chunked
                                        */
    SEC2_DPD                 **Dpds;         /* Array of pointers to DPDs that can
                                        used when generating DPD requests

                                        #MAX_DPDS identifies
                                        how many DPDs are allocated during
                                        startup.
                                        */
} SEC2_CHANNEL_ASSIGNMENT;

/*  A double linked list to pending dynamic requests */
typedef struct queue_entry
{
    int                 requestingTaskId;   /* Requesting task's Id.

                                            This becomes
                                            channel_assignment::ownerTaskId
                                            when a channel can be assigned.
                                            */
   /* int                 chan; */              /*没有用到 channel if static
                                            be free before the entry can
                                            be assigned to a channel
                                            */
    GENERIC_REQ         *pReq;              /* Pointer to the start of a
                                            linked list describing the request

                                            This becomes
                                            channel_assignment::pReq
                                            when a channel can be assigned.
                                            */
    DPD_DETAILS_ENTRY   *pDesc;
    struct queue_entry  *next;              /* pointer to next entry */
    struct queue_entry  *previous;          /* pointer to previous entry */
} QUEUE_ENTRY;

typedef struct sec2_fwd_queue
{
    int                 num;
    int                 requestingTaskId;   /* Requesting task's Id.
                                            This becomes
                                            channel_assignment::ownerTaskId
                                            when a channel can be assigned.
                                            */
    int                 used;
    int                 status;             /*纪录状态*/                                        
    GENERIC_REQ         *pReq;              /* Pointer to the start of a
                                            linked list describing the request

                                            This becomes
                                            channel_assignment::pReq
                                            when a channel can be assigned.
                                            */
    struct sec2_fwd_queue  *next;            /* pointer to next entry */
} SEC2_FWD_QUEUE;

typedef struct sec2_Device
{
    char rxFwdFlag;   /*The flag used to flag the status of FWD TASK ring */
}DRV_SEC2_END;

typedef enum
{
   SEC2_PKT_UNUSED_FLAG         = 0x00,
   SEC2_PKT_USED_FLAG           = 0x01,
}SEC2_FWD_QUEUE_ONWER;

typedef struct fwd_queue_entry
{
    int                 requestingTaskId;   /* Requesting task's Id.

                                            This becomes
                                            channel_assignment::ownerTaskId
                                            when a channel can be assigned.
                                            */
    UINT32              owner;              /*Refer to SEC2_FWDQ_OWNER_TYPE
											*/
    GENERIC_REQ         *pReq;              /* Pointer to the start of a
                                            linked list describing the request

                                            This becomes
                                            channel_assignment::pReq
                                            when a channel can be assigned.
                                            */
    struct queue_entry  *next;              /* pointer to next entry */
} FWD_QUEUE_ENTRY;

typedef struct
{
   unsigned long channel_DynamicCnt;
   unsigned long channel_WaitCnt;
   unsigned long channel_SuccCnt;
   unsigned long channel_ErrCnt;
}SEC2_CHANNEL_PKTCNT_DEBUG;

typedef struct
{
    unsigned long pkt_in;
	unsigned long isr_out;
	                                             /*yuhongtao 2007-04-24*/
    unsigned long unknown_isr_cnt;  /*无效的中断，出现的情况:CPU电平波动，状态寄存器错误*/
    unsigned long last_status0;
    unsigned long last_status1;
}SEC2_PKTCNT_DEBUG;

extern SEC2_CHANNEL_PKTCNT_DEBUG*  pgsec2_channel_debug;
extern SEC2_PKTCNT_DEBUG        *  pgsec2_global_debug;

/* (!sec) these may be obsolete */
#define ALL_INT_ERRORS_MASK_LOW ((unsigned long)0x000000ff)
#define ALL_INT_ERRORS_MASK_HIGH ((unsigned long)0x00333333)