sec2driver.h

freescale ppc sec2加解密单元驱动

/****************************************************************************
 * Sec2Driver.h - Private/local include file for SEC2 security driver
 ****************************************************************************
 * Copyright (c) 2003, 2004 Freescale Semiconductor
 * All Rights Reserved. Proprietary and Confidential.
 *
 * NOTICE: The information contained in this file is proprietary
 * to Freescale Semiconductor, and is being made available to
 * Freescale's customers under strict license agreements.
 * Use or disclosure of this information is permissible only
 * under the terms of the existing license agreement.
 ***************************************************************************/


/* Revision History:
 * 1.0   Aug 24,2003 dgs adapted from the final version of mpc18x
 *       May 12,2004 sec - moved interrupt assign for MPC8555
 *       May 26,2004 sec - add support for scatter buffers
 *       Aug 27,2004 sec - fixed channel interrupt masks
 * 1.1.0 Nov 05,2004 sec - integrate/merge linux changes from prior revs
 * 1.2   Jan 27,2005 sec - move global inhibit bit
 */

#ifndef SEC2DRIVER_H
#define SEC2DRIVER_H
#define DRIVER_IPSEC_DBG 0
#ifdef __KERNEL__
#include <linux/module.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <asm/uaccess.h>
#include <asm/atomic.h>
#include <asm/semaphore.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/io.h>

#undef malloc
#undef free
#define free kfree
#define malloc(a) kmalloc(a, GFP_KERNEL)
#undef semGive
#undef semTake
#define semDelete(x)
#define semGive(a) up(&a)
#define semTake(a, b) down_interruptible_timeout(&a, b)

extern long __down_interruptible_timeout(struct semaphore *sem, long timeout);
extern inline int down_interruptible_timeout(struct semaphore *sem, long timeout)
{
    int ret = 0;
#if WAITQUEUE_DEBUG
    CHECK_MAGIC(sem->__magic);
#endif
    
    if (atomic_dec_return(&sem->count) < 0)
        ret = __down_interruptible_timeout(sem, timeout);
    
    smp_wmb();
    return ret;
}

#define taskIdSelf() current->pid
#define __vpa(va) ((pte_val(*pte_offset(pmd_offset(pgd_offset_k(va), (va)), (va))) & PAGE_MASK) + (va & ~PAGE_MASK))
#define SEC2_DEVMAJOR 0
#else /* assume VXWORKS */

#include "vxWorks.h"
#include "iosLib.h"
#include "msgQLib.h"
#include "stdlib.h"
#include "semLib.h"
#include "time.h"
#include "string.h"
#include "taskLib.h"
#include "cacheLib.h"
#include "signal.h"
#include "driver/drvlib/include/drv_comm.h"

#define IVEC_TO_INUM(intVec)    ((int) (intVec))
#define INUM_TO_IVEC(intNum)    ((VOIDFUNCPTR *) (intNum))

#define __vpa(pa) (pa)
#endif

/*  NUM_DPD_FLDS
    Number of fields in a ::dpd
*/
#define NUM_DPD_FLDS    7

#include "Sec2.h"
#include "ipsec_request.h"
#include "sec2_dpd_table.h"
#include "target/mp/8349/bsp/ads834x.h"
#define VERSION "1.2"

#define SEC2_DEVNAME "sec2"

/* This might move out to a board-specfic header somewhere, */
/* not a core-specific header such as this */
#define INUM_SEC2 0x29  /* SEC core is wired to #29 within the MPC8555 */

/* Define an offset from the peripheral base register where the core */
/* should be located relative to */
#define TALITOS2X_BASE_ADDRESS (UINT32)(0x00030000)

/* Define the size of the register region */
#define SEC2_BASE_SIZE (0x10000)


/* When static scatter pool fully functional, define here */
/* Else, use dynamic pool                                 */
#define DYNAMIC_SCATTER_POOL


/* Do right-justifies output shift for PKHA results due to errata */
#define PKHA_OUTPUT_SHIFT 0


/* 
 * Debug message type enabler switches for SEC2DebugLevel:
 * DBGTXT_SETRQ   - all messages from request setups
 * DBGTXT_SVCRQ   - all messages from request servicing
 * DBGTXT_INITDEV - all messages from initialization
 * DBGTXT_DPDSHOW - content of each DPD before it's queued
 * DBGTXT_INFO    - general driver information messages
 */
 
#if DRIVER_IPSEC_DBG
#define DBGTXT_SETRQ              ((unsigned long)0x00000001)
#define DBGTXT_SVCRQ              ((unsigned long)0x00000002)
#define DBGTXT_INITDEV            ((unsigned long)0x00000004)
#define DBGTXT_DPDSHOW            ((unsigned long)0x00000008)
#define DBGTXT_INFO               ((unsigned long)0x00000010)
extern unsigned long SEC2DebugLevel;

#ifdef VXWORKS
#define SEC2Dump(LEVEL,STRING) \
        do { \
            unsigned long _level = (LEVEL); \
            if ((_level == 0)||(SEC2DebugLevel & _level)) { \
                printf STRING; \
            } \
        } while (0)
#else
#define SEC2Dump(LEVEL,STRING) \
        do { \
            unsigned long _level = (LEVEL); \
            if ((_level == 0)||(SEC2DebugLevel & _level)) { \
                printk STRING; \
            } \
        } while (0)
#endif


#else   /* ndef DBG */
#define SEC2Dump(LEVEL,STRING)
#endif  /* DBG */



#ifdef VXWORKS
#define IOLockChannelAssignment() (void) semTake(sec2_ChannelAssignSemId, WAIT_FOREVER)
#define IOUnLockChannelAssignment() (void) semGive(sec2_ChannelAssignSemId)
#endif

#ifdef __KERNEL__
extern unsigned long irq_flag;

#define IOLockChannelAssignment() spin_lock_irqsave(&ChannelAssignLock,irq_flag)
#define IOUnLockChannelAssignment() spin_unlock_irqrestore(&ChannelAssignLock,irq_flag)

#define M_ioLib (12 << 16)
#define S_ioLib_UNKNOWN_REQUEST (M_ioLib | 2)

typedef long DEV_HDR;

#endif



#define IO_STATUS                 int
#define MAX_DPDS                  (24)
#define SEC2_HANDLE_QUEUE_DEPTH   (64)
#define SEC2_FWD_QUEUE_DEPTH      (128)

/* internal flag for pointer register - indirect pointer */
#define PTRTYPE_JBIT           (0x00008000)


/* SEC2_MASTER_CONTROL_REGISTER - Master Control Register offset */
#define SEC2_MASTER_CONTROL_REGISTER     ((unsigned long)0x00001030)

/* SEC2_RESET - software-controller reset of the SEC2 core */
#define SEC2_RESET          ((unsigned long)0x00000001)

/* SEC2_GLOBAL_INHIBIT - */
#define SEC2_GLOBAL_INHIBIT ((unsigned long)0x00000002)



/*! \def MAX_MESSAGES
    \brief (VxWorks Only) Queue Length for Isr queue represented
    by global variale #IsrMsgQId
*/
#define MAX_MESSAGES (40)

/*! \def PROCESSING_COMPLETE_PRIORITY
    \brief (VxWorks Only) #Sec2_ProcessingComplete() Task priority
*/
#define PROCESSING_COMPLETE_PRIORITY (3)

/*! \def PROCESSING_COMPLETE_STACKSIZE
    \brief (VxWorks Only) #Sec2_ProcessingComplete() Task stack size
*/
#define PROCESSING_COMPLETE_STACKSIZE (2048)

/*! \def CHANNEL_FREE
    \brief Channel is available

    Indicates that the channel assignment is FREE or available.
*/
#define CHANNEL_FREE (unsigned char) (0)
/*! \def CHANNEL_DYNAMIC
    \brief Channel is assigned as dynamic

    Indicates that the channel assignment is dynamic.
    A process is in the middle of performing a dynamic operation.
*/
#define CHANNEL_DYNAMIC (unsigned char) (1)
#define CHANNEL_WAIT       (unsigned char)(2)
/*! \def CHA_DYNAMIC
    \brief The CHA is available for dynamic acquisition

    This applies to the #ChaAssignments array.  Any element in this
    array that is set to CHA_DYNAMIC means that the CHA represented
    by the array index is available
*/
#define CHA_DYNAMIC (0)

#define CHA_DES  (0)
#define CHA_AESA (1)
#define CHA_MDHA (2)  
#define CHA_AFHA (3)
#define CHA_RNG  (4)
#define CHA_PKHA (5)  
#define CHA_MDHA_DES (106)
#define CHA_MDHA_AES (105)


/*! \def CHA_AFHA_BITMASK
    \brief An internal bitmask representation for an ARC4 CHA
*/
#define CHA_AFHA_BITMASK (0x1)
/*! \def CHA_DESA_BITMASK
    \brief An internal bitmask representation for a DES CHA
*/
#define CHA_DESA_BITMASK (0x2)
/*! \def CHA_MDHA_BITMASK
    \brief An internal bitmask representation for an MD CHA
*/
#define CHA_MDHA_BITMASK (0x4)
/*! \def CHA_RNGA_BITMASK
    \brief An internal bitmask representation for an RNG CHA
*/
#define CHA_RNGA_BITMASK (0x8)
/*! \def CHA_PKHA_BITMASK
    \brief An internal bitmask representation for a PK CHA
*/
#define CHA_PKHA_BITMASK (0x10)
/*! \def CHA_AESA_BITMASK
    \brief An internal bitmask representation for a AESA CHA
*/
#define CHA_AESA_BITMASK (0x20)
/*! \def CHA_KEA_BITMASK
    \brief An internal bitmask representation for a KEA CHA
*/
#define CHA_KEA_BITMASK (0x40)


/*! \def DES_BLOCK
    \brief Size of DES block
*/
#define DES_BLOCK (8)
/*! \def ARC4_MIN_KEYBYTES
    \brief Minimum ARC4 key length
*/
#define ARC4_MIN_KEYBYTES (1)
/*! \def ARC4_MAX_KEYBYTES
    \brief Maximum ARC4 key length
*/
#define ARC4_MAX_KEYBYTES (16)
/*! \def ARC4_CONTEXTBYTES
    \brief Context length for ARC4
*/
#define ARC4_CONTEXTBYTES (259)

/*! \def DOUBLE_WORD_ALIGNMENT
    \brief Mask to be applied to address in order to determine
    if it is double word aligned or not
*/
#ifdef NO_DOUBLE_WORD_ALIGNMENT
#define DOUBLE_WORD_ALIGNMENT ((unsigned long)0x00000000)
#else
#define DOUBLE_WORD_ALIGNMENT ((unsigned long)0x00000007)
#endif

/*! \def IO_BASE_ADDRESS_MASK
    \brief Mask to be applied to base address value return from IO
    bus
*/
#define IO_BASE_ADDRESS_MASK ((unsigned long)0xFFFE0000)

/*! \def INTERRUPT_CONTROL_OFFSET
    \brief Offset for the Interrupt Control Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_InterruptControlRegister variable during Driver Startup
*/
#define INTERRUPT_CONTROL_OFFSET ((unsigned long)0x00001008)

/*! \def INTERRUPT_STATUS_OFFSET
    \brief Offset for the Interrupt Status Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_InterruptStatusRegister variable during Driver Startup
*/
#define INTERRUPT_STATUS_OFFSET ((unsigned long)0x00001010)

/*! \def INTERRUPT_CLEAR_OFFSET
    \brief Offset for the Interrupt Clear Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #sec2_InterruptClearRegister variable during Driver Startup
*/
#define INTERRUPT_CLEAR_OFFSET ((unsigned long)0x00001018)

/*! \def IDENTIFICATION_OFFSET
    \brief Offset for the ID Register.
    
    This is relative to the base address register for the
    SEC2 coprocessor.  It is used to setup the
    #IDRegister variable during Driver Startup
*/
#define IDENTIFICATION_OFFSET ((unsigned long)0x00001020)

/* Possible core ID mask values */