le1vefpgalib.c

Zalink50114----TDMoIP芯片驱动源码

/* le1veFpgaLib.c - LE1VE (TDMoIP) FPGA interfdace resoure libary file
*
* Copyright     2004-2007 ZTE, Inc.
* author:       ZhengQishan
* date:         2004.02
*
* modification history
*------------------------------
* 2004-07-28 FPGA所实现的PCI控制器不支持burst方式访问，所以不能对PCI连续地址访问
*
*/
#include "le1veFpgaLib.h"
extern SEM_ID drv_ReadRegSemaphore[];

int readerrcount = 0;
int writeerrcount = 0;
/*ZL50114使用Motorola类型的HOST总线, 数据宽度为32位, 地址位22位,
操作方式为同步, 与GAR系统使用的通用CPU总线有比较大的差别, 所以需要
FPGA进行访问转换*/

/*----------------------------
写操作
a)	首先读取cpu_ctl_reg[7], 判断是否可以进行操作.
b)	设置cpu_data_reg[31:0]与cpu_addr_reg[23:0]
c)	将cpu_ctl_reg[0]置1, 即可完成本次写操作
*/
void ZL5011X_REG_WRITE(int slot, UINT32 reg, UINT32 value)
{
	UINT32  regAddr;
	UINT32  tempState;
	int     loop = 0;

    semTake(drv_ReadRegSemaphore[slot - 1], WAIT_FOREVER);
	regAddr = IF_CARD_CPU_REG_BASE(slot);
	do{
		tempState = *(volatile UINT32 *)(regAddr + FPGA_CONTROL_REG);
		tempState = Drv_Swap32(tempState);
		loop ++;
	}while((0 != (FPGA_CTRL_WR_BUSY & tempState)) && (loop < FPGA_WR_RD_TIMEOUT));

	if (loop >= FPGA_WR_RD_TIMEOUT)
	{
        if (FPGA_CTRL_RD_WR_TIMEOUT == (tempState & FPGA_CTRL_RD_WR_TIMEOUT))
            logMsg("ZL50114 register write time out!\n",0,0,0,0,0,0);
		taskSuspend(0);
	}

    loop = 0;
    do{
	*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG1) = Drv_Swap32(((reg) >> 8) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG0) = Drv_Swap32((reg) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG2) = Drv_Swap32(((reg) >> 16) & 0xff);
        if(loop >0)
            writeerrcount++;
        loop ++;
      }while(((Drv_Swap32(*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG1)) & 0xFF) != ((reg >> 8) & 0xff) ||
          (Drv_Swap32(*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG0))& 0xFF) != ((reg) & 0xff) ||
          (Drv_Swap32(*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG2))& 0xFF) != ((reg >> 16) & 0xff ))&& (loop < FPGA_WR_RD_TIMEOUT)
      );
      
	*(volatile UINT32 *)(regAddr + FPGA_DATA_REG0) = Drv_Swap32((value) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_DATA_REG2) = Drv_Swap32(((value) >> 16) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_DATA_REG1) = Drv_Swap32(((value) >> 8) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_DATA_REG3) = Drv_Swap32(((value) >> 24) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_CONTROL_REG) = Drv_Swap32(FPGA_CTRL_WRI_ENABLE);
    semGive(drv_ReadRegSemaphore[slot - 1]);
}
/*------------------------
读操作
a)	首先读取cpu_ctl_reg[7], 判断是否可以进行操作.
b)	设置cpu_addr_reg[23:0].
c)	将cpu_ctl_reg[1]置1, 等待一段时间,该时间与访问目标有关.
d)	读取cpu_ctl_reg[6], 如果为1, cpu_data_reg[31:0]中就是目标数据
*/
void ZL5011X_REG_READ(int slot, UINT32 reg, volatile UINT32 *value)
{
	UINT32  regAddr;
	UINT32  tempState;
	int loop = 0;

    semTake(drv_ReadRegSemaphore[slot - 1], WAIT_FOREVER);
	regAddr = IF_CARD_CPU_REG_BASE(slot);
	do{
		tempState = *(volatile UINT32 *)(regAddr + FPGA_CONTROL_REG);
		tempState = Drv_Swap32(tempState);
		loop ++;
	}while((0 != (FPGA_CTRL_WR_BUSY & tempState)) && (loop < FPGA_WR_RD_TIMEOUT));
	if (loop >= FPGA_WR_RD_TIMEOUT)
	{
        if (FPGA_CTRL_RD_WR_TIMEOUT == (tempState & FPGA_CTRL_RD_WR_TIMEOUT))
            logMsg("ZL50114 register read time out!\n",0,0,0,0,0,0);
		taskSuspend(0);
	}
    
    loop = 0;
    do{
	*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG1) = Drv_Swap32(((reg) >> 8) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG0) = Drv_Swap32((reg) & 0xff);
	*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG2) = Drv_Swap32(((reg) >> 16) & 0xff);
        if(loop > 0)
            readerrcount++;
        loop ++;
    }while(((Drv_Swap32(*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG1)) & 0xFF) != ((reg >> 8) & 0xff) ||
          (Drv_Swap32(*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG0))& 0xFF) != ((reg) & 0xff) ||
          (Drv_Swap32(*(volatile UINT32 *)(regAddr + FPGA_ADDR_REG2))& 0xFF) != ((reg >> 16) & 0xff ))&& (loop < FPGA_WR_RD_TIMEOUT)
      );
	*(volatile UINT32 *)(regAddr + FPGA_CONTROL_REG) = Drv_Swap32(FPGA_CTRL_RD_ENABLE);


	loop = 0;
	do{
		tempState = *(volatile UINT32 *)(regAddr + FPGA_CONTROL_REG);
		tempState = Drv_Swap32(tempState);
		loop ++;
	}while((FPGA_CTRL_RD_READY != (FPGA_CTRL_RD_READY & tempState)) && (loop < FPGA_WR_RD_TIMEOUT));
	if (loop >= FPGA_WR_RD_TIMEOUT)
	{
        if (FPGA_CTRL_RD_WR_TIMEOUT == (tempState & FPGA_CTRL_RD_WR_TIMEOUT))
            logMsg("ZL50114 register read time out!\n",0,0,0,0,0,0);
		taskSuspend(0);
	}
	tempState = *(volatile UINT32 *)(regAddr + FPGA_DATA_REG0);
	*value = Drv_Swap32(tempState) & 0xFF;
	tempState = *(volatile UINT32 *)(regAddr + FPGA_DATA_REG1);
	*value |= (Drv_Swap32(tempState) & 0xFF) << 8;
	tempState = *(volatile UINT32 *)(regAddr + FPGA_DATA_REG2);
	*value |= (Drv_Swap32(tempState) & 0xFF) << 16;
	tempState = *(volatile UINT32 *)(regAddr + FPGA_DATA_REG3);
	*value |= (Drv_Swap32(tempState) & 0xFF) << 24;
    semGive(drv_ReadRegSemaphore[slot - 1]);
}