le1vediag.c

Zalink50114----TDMoIP芯片驱动源码

	 sprintf((buffer+strlen(buffer)),"Tmi_ovf_Msk(0x60010):\t %08x\tTask manager interface overflow mask\n",value);
	 ZL5011X_REG_READ(slotNum, ZL5011X_PLA_BASE + 0x60018, &value);
	 sprintf((buffer+strlen(buffer)),"cxt_err_clear(0x60018):\t %08x\tWrite in zero, prior to reading Context error memory\n",value);
	 
	 sprintf((buffer+strlen(buffer)),"Zl5011x TIF Block key Register Value:\t\n");
	 ZL5011X_REG_READ(slotNum, ZL5011X_TIF_BASE + 0x0, &value);
	 sprintf((buffer+strlen(buffer)),"TIF Control(0x60008):\t %08x\tDefines the operational modes for the TDM inputs and outputs\n",value);

	 sprintf((buffer+strlen(buffer)),"Zl5011x TM Block key Register Value:\t\n");
	 ZL5011X_REG_READ(slotNum, ZL5011X_TM_BASE + 0x44, &value);
	 sprintf((buffer+strlen(buffer)),"TM_clear_int_reg(0x44):\t %08x\tTM Interrupt Clear register\n",value);
	 ZL5011X_REG_READ(slotNum, ZL5011X_PLA_BASE + 0x84, &value);
	 sprintf((buffer+strlen(buffer)),"TM_mask_int_reg(084):\t %08x\tTM Interrupt Mask register\n",value);
	 ZL5011X_REG_READ(slotNum, ZL5011X_PLA_BASE + 0xc0, &value);
	 sprintf((buffer+strlen(buffer)),"TM_int_reg(0xc0):\t %08x\tTM Interrupt register 'raw'\n",value);
	 ZL5011X_REG_READ(slotNum, ZL5011X_PLA_BASE + 0xc4, &value);
	 sprintf((buffer+strlen(buffer)),"TM_int_poll_reg(0xc4):\t %08x\tTM Interrupt Status register\n",value);

     if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
     {
         sprintf((buffer+strlen(buffer)),"========\tEnd Slot %d E1VE Card\t========%d\n",slotNum,(int)strlen(buffer));
     }
     else
     {
         sprintf((buffer+strlen(buffer)),"========\tEnd Slot %d T1VE Card\t========%d\n",slotNum,(int)strlen(buffer));
     }
     return OK;
}
/******************************************************
 Function:
  drv_le1veShowCpld()

 Description:
  打印E1VE板CPLD 基本信息
 Inputs:
  slotNum 槽位号
  buffer 回显字符串指针
 Outputs:
  buffer 

 Returns:
   OK or ERROR
 Remarks:
  *******************************************************/
int drv_le1veShowCpld(int slotNum, char *buffer)
{
    int i=0;
	int value=0;
    if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
    {
        sprintf(buffer,"\n========\tSlot: %d E1VE Card CPLD\t ========\n",slotNum);
    }
    else
    {
        sprintf(buffer,"\n========\tEnd Slot: %d T1VE Card CPLD\t========\n",slotNum);
    }
    for(i=0;i<0x1b;i++)
    {
        if(0 ==(i % 16))
	        sprintf((buffer+strlen(buffer)),"\n%08x:",i);
		value = drv_cpldRegRead(slotNum,4*(LE1VE_CPLD_OFFSET+i));
		sprintf((buffer+strlen(buffer)),"%02x ", value & 0xFF);
    }
	sprintf((buffer+strlen(buffer)),"\ninterface_type_addr(0x00) \t\tinterface_sub_type_addr(0x01)\n");
    sprintf((buffer+strlen(buffer)),"cpld_version_addr(0x02) \t\tdevice_id_addr(0x03)\n");
	sprintf((buffer+strlen(buffer)),"interrupt_state_addr(0x05) \t\tinterrupt_indicate_addr(0x06)\n");
    sprintf((buffer+strlen(buffer)),"interrupt_mask_addr(0x07)\t:0-enable 1-disable \nimpedance_switch_addr(0x08)\t:0-75 1-210\n");
    sprintf((buffer+strlen(buffer)),"dm_ctl_addr(0x13)\t\t:0-4354 TDM 1-BACkPLANE TDM\nadaptive_clock_addr(0x1a)\t:0-disable 1-enable\n");	
	sprintf((buffer+strlen(buffer)),"H-MVIP_16M_clock(0x1b)\t: 1-line_refclk 2-TMV-8dc 3-local 16M \n");
	if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
    {
        sprintf((buffer+strlen(buffer)),"========\tSlot: %d E1VE Card CPLD\t ========\n",slotNum);
    }
    else
    {
        sprintf((buffer+strlen(buffer)),"========\tEnd Slot: %d T1VE Card CPLD\t========\n",slotNum);
    }
	return OK;
}
/******************************************************
 Function:
  drv_le1veShowFpga()

 Description:
  打印E1VE板FPGA 基本信息
 Inputs:
  slotNum 槽位号
  buffer 回显字符串指针
 Outputs:
  buffer 

 Returns:
   OK or ERROR
 Remarks:
  *******************************************************/
int drv_le1veShowFpga(int slotNum, char *buffer)
{
	LE1VE_PCI_DRV_CTRL  *pDrv =NULL;
    int i=0;
	int value =0;
    if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
    {
        sprintf(buffer,"\n========\tSlot: %d E1VE Card FPGA\t ========\n",slotNum);
    }
    else
    {
        sprintf(buffer,"\n========\tSlot: %d T1VE Card FPGA\t========\n",slotNum);
    }
    for(i=0;i<0xB;i++)
    {
        if(0 ==(i % 16))
	        sprintf((buffer+strlen(buffer)),"\n%08x:",i);
		value = drv_fpgaRegRead(slotNum,4*(LE1VE_FPGA_OFFSET+i));
		sprintf((buffer+strlen(buffer)),"%02x ", value & 0xFF);
    }
    sprintf((buffer+strlen(buffer)),"\nVersion_reg(0x00)\t: Bit[3:0]-sub version\tBit[7:4]-major version \n");
    sprintf((buffer+strlen(buffer)),"DeviceID_reg(0x01)\n");
	sprintf((buffer+strlen(buffer)),"Down_succ_reg0(0x02)\t: 0x55 for success\n");
    sprintf((buffer+strlen(buffer)),"Down_succ_reg1(0x03)\t: 0xAA for success\n");
    sprintf((buffer+strlen(buffer)),"Cpu_ctl_reg(0x03)\t: Bit[0]: 1-write enable \t\tBit[1]: 1-read enalbe\n");
	sprintf((buffer+strlen(buffer)),"\t\t\t  Bit[5]: 1-operation time over\t\tBit[6]: 1-data ready\n\t\t\t  Bit[7]: 0-bus free 1--bus busy\n");
	sprintf((buffer+strlen(buffer)),"Cpu_addr_reg\t: Bit[23:0] composed by reg(0x04)[0-7] and reg(0x05)[8-15] and reg(0x06)[16-23]\n");
	sprintf((buffer+strlen(buffer)),"Cpu_data_reg\t: Bit[31:0] composed by reg(0x07)[0-7] and reg(0x08)[8-15] and reg(0x09)[16-23] \n\t\t  and reg(0x10)[24-32]\n");
    sprintf((buffer+strlen(buffer)),"\nFPGA PCI Registers:\n");
	pDrv = (LE1VE_PCI_DRV_CTRL  *)gpLe1veDrvCtrl[slotNum - 1];
	if(NULL != pDrv)
	{
	    sprintf((buffer+strlen(buffer)),"Up BD table base addr\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->rxDescBase)));
	    sprintf((buffer+strlen(buffer)),"Down BD table base addr\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->txDescBase)));
	    sprintf((buffer+strlen(buffer)),"BD table Number\t\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->descNum)));
	    sprintf((buffer+strlen(buffer)),"PCI Interrupt State\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->pciIntState)));
	    sprintf((buffer+strlen(buffer)),"PCI Interrupt Mask\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->pciIntMask)));
	    sprintf((buffer+strlen(buffer)),"Up Enable\t\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->rxEnable)));
        sprintf((buffer+strlen(buffer)),"Down Enable\t\t:%08x\n",Drv_Swap32(mapPhysToVirt(pDrv->pMem->txEnable)));
	}
	if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
    {
        sprintf((buffer+strlen(buffer)),"========\tSlot: %d E1VE Card FPGA\t ========\n",slotNum);
    }
    else
    {
        sprintf((buffer+strlen(buffer)),"========\tSlot: %d T1VE Card FPGA\t========\n",slotNum);
    }
    return OK;   
}

/******************************************************
 Function:
  drv_le1veShowBuffer()

 Description:
  打印E1VE板BUFFER 基本信息
 Inputs:
  slotNum 槽位号
  buffer 回显字符串指针
 Outputs:
  buffer 

 Returns:
   OK or ERROR
 Remarks:
  *******************************************************/
int drv_le1veShowBuffer(int slotNum, char *buffer)
{
	LE1VE_PCI_DRV_CTRL  *pDrv =NULL;

    if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
    {
        sprintf(buffer,"\n========\tSlot: %d E1VE Card BUFFER\t ========\n",slotNum);
    }
    else
    {
        sprintf(buffer,"\n========\tSlot: %d T1VE Card BUFFER\t========\n",slotNum);
    }
	pDrv = gpLe1veDrvCtrl[slotNum - 1];
    if(NULL != pDrv)
    {
	    drv_le1veBDShow(pDrv, (buffer+strlen(buffer)));
    }
    if(CARD_TMD_OVER_IP_4_1 == b_physIfType(slotNum))
    {
        sprintf((buffer+strlen(buffer)),"========\tEnd Slot: %d E1VE Card BUFFER\t ========\n",slotNum);
    }
    else
    {
        sprintf((buffer+strlen(buffer)),"========\tEnd Slot: %d T1VE Card BUFFER\t========\n",slotNum);
    }

    return OK;
}

/******************************************************
 Function:
  diag_prjLe1veParse()

 Description:
  E1VE诊断参数解析函数
 Inputs:
  pMsg OAM消息
  pLe1veParam 项目诊断参数
 Outputs:

 Returns:
   OK or ERROR
 Remarks:
  *******************************************************/
int diag_prjLe1veParse(MSG_COMM_OAM       *pMsg, diagPrjParam *pLe1veParam)
{
   OPR_DATA *pData = (OPR_DATA *)pMsg->Data;
   DIAG_TRACE(DIAG_NORMAL_FN_ID,"diag_prjLe1veParse --",0,0,0,0,0,0);
   if(NULL== pMsg || NULL == pLe1veParam)
   {
      DIAG_TRACE(DIAG_ERR_FN_ID,"diag_prjLe1veParse --Null Pointer",0,0,0,0,0,0);
      return ERROR;
   }
   pLe1veParam->IntfCard.diagSubType = DIAG_TYPE_GET(pMsg->CmdID);
   pLe1veParam->IntfCard.slotNum= *(pData->Data);
   return OK;   
}
/******************************************************
 Function:
  drv_le1veDiag()

 Description:
  E1VE诊断入口函数
 Inputs:
  pdiagPrjParam 诊断参数指针
  ret_buffer 回显字符串指针
 Outputs:
  *ret_buffer 

 Returns:
   OK or ERROR
 Remarks:
  *******************************************************/
int drv_le1veDiag(diagPrjParam *pdiagPrjParam, char **ret_buffer)
{
     char  *tempbuf= NULL;
     if(NULL ==(tempbuf = DIAG_ALLOC(DIAG_BUFFER_SIZE)))
     {
         return ERROR;
     }
	 memset(tempbuf,0,DIAG_BUFFER_SIZE);
    /*分配内存*/
    switch(pdiagPrjParam->IntfCard.diagSubType)
    {
            case DIAG_PRJ_CARD_CLOCKINTFO:
		        le1veDignoseDisplayClockinfo(pdiagPrjParam->IntfCard.slotNum, tempbuf);
			   break;
         case DIAG_PRJ_CARD_BASICINFO:
			drv_le1veShowCardInfo(pdiagPrjParam->IntfCard.slotNum, tempbuf);
			break;
	     case DIAG_PRJ_CARD_CPLD:
	 	       drv_le1veShowCpld(pdiagPrjParam->IntfCard.slotNum, tempbuf);
	 	       break;
	     case DIAG_PRJ_CARD_FPGA:
	 	       drv_le1veShowFpga(pdiagPrjParam->IntfCard.slotNum, tempbuf);
	 	       break;
	     case DIAG_PRJ_CARD_BUFFER:
	 	       drv_le1veShowBuffer(pdiagPrjParam->IntfCard.slotNum, tempbuf);
	 	       break;
	         default :
		       break;
    }
    (*ret_buffer) = tempbuf; 
    return OK;
}

int drv_le1veRegister(int slotNum)
{
    return  diag_prjIntfCardCtrlRegist(slotNum, diag_prjLe1veParse, drv_le1veDiag);
}
/********  test function ******/
int test_le1vebuffer(int slot)
{
   char *buffer =NULL;
   LE1VE_PCI_DRV_CTRL * pDrv =NULL;
   if(slot <1 || slot >8)
     return ERROR;
   if(NULL == (buffer = DIAG_ALLOC(DIAG_BUFFER_SIZE)))
   {
      return ERROR;
   }
   pDrv = (LE1VE_PCI_DRV_CTRL  *)gpLe1veDrvCtrl[slot - 1];
   drv_le1veBDShow(pDrv,buffer);
   printf("%s",buffer);
   DIAG_FREE(buffer);
   return OK;
}