📄 zl5011xpacmap.h
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/*******************************************************************************
*
* File name: zl5011xPacMap.h
*
* Version: 22
*
* Author: MRC
*
* Date created: 27/03/2002
*
* Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
* All rights reserved.
*
* Module Description:
*
* This is the register definitions header file for PAC block.
* It contains the register offsets and bit field definitions.
*
* Revision History:
*
* Rev: Date: Author: Comments:
* 1 27/03/2002 MRC Creation
* 2 28/03/2002 MRC Added async functions
* 3 03/04/2002 MRC Update
* 4 16/04/2002 MRC Changed Authur to Author in the header
* 5 15/05/2002 MRC Minor PAC address map changes
* 6 23/05/2002 MRC Async reference and RTP had changed in the PAC
* 7 17/06/2002 LCW Update
* 8 19/06/2002 MRC PAC block changed
* 9 09/07/2002 MRC Update
* 10 15/07/2002 MRC DCO registers changed
* 11 16/09/2002 MRC Added in fns for setting inverse DCO value
* 12 19/09/2002 MRC Added extra dpll control fns
* 13 31/10/2002 MRC Added variants + minor fixes
* 14 11/11/2002 MRC Modified interrupt mask bits
* 15 28/01/2003 MRC Added defines for CET data collection
* 16 06/02/2003 MRC DPLL mode bits changed in spec
* 17 07/02/2003 MRC Fixed define for RTP PRS frequency mask
* 18 24/03/2003 MRC Changed slew rate limit defaults
* 19 22/05/2003 NJF Changes for B-rev PAC
* 20 27/05/2003 MRC Tidied up PAC changes and enable TDL's
* 21 07/10/2003 MRC Increased the maximum In-band PRS frequency
* 22 21/07/2005 MRC Moved PLL status bits to file zl5011xPac.h
*
*******************************************************************************/
#ifndef _ZL5011X_PAC_MAP_H
#define _ZL5011X_PAC_MAP_H
#ifdef __cplusplus
extern "C" {
#endif
/* default values for the DCO delay line settings */
#define ZL5011X_PAC_ASYNC_DEFAULT_TDL_FILTER 0
#define ZL5011X_PAC_SYNC_DEFAULT_TDL_FILTER 0
/* constants for the DPLL */
#define ZL5011X_DPLL_TARGET_FREQ_KHZ (Uint32T)65536
#define ZL5011X_DPLL_MAX_LOCK_RANGE_PPM (Uint32T)500
#define ZL5011X_DPLL_DEFAULT_SLEW_RATE (Uint32T)0x99f
#define ZL5011X_DPLL_DEFAULT_BANDWIDTH (Uint32T)2
/* constants for the DCO */
#define ZL5011X_DCO_MAX_OFFSET_PPM (Uint32T)250
/******************************************************************************
* DPLL definitions
******************************************************************************/
/* setup the offset from the PAC base address for the DPLL sub-block */
#define ZL5011X_DPLL_BASE ZL5011X_PAC_BASE + 0x200
/* addresses of registers for the DPLL block */
#define ZL5011X_DPLL_CONTROL ZL5011X_DPLL_BASE + 0x00000
#define ZL5011X_DPLL_CENTRE_FREQ ZL5011X_DPLL_BASE + 0x00004
#define ZL5011X_DPLL_INVERSE_CENTRE_FREQ ZL5011X_DPLL_BASE + 0x00008
#define ZL5011X_DPLL_INVERSE_T1_FREQ ZL5011X_DPLL_BASE + 0x0000c
#define ZL5011X_DPLL_INVERSE_J2_FREQ ZL5011X_DPLL_BASE + 0x00010
#define ZL5011X_DPLL_LOCK_RANGE ZL5011X_DPLL_BASE + 0x00018
#define ZL5011X_DPLL_LOCK_DETECT ZL5011X_DPLL_BASE + 0x0001c
#define ZL5011X_DPLL_SLEW_RATE ZL5011X_DPLL_BASE + 0x00020
#define ZL5011X_DPLL_CHANGE_CONTROL ZL5011X_DPLL_BASE + 0x00024
#define ZL5011X_DPLL_CHANGE_STATUS ZL5011X_DPLL_BASE + 0x00028
#define ZL5011X_DPLL_CHK_SINGLE_PERIOD ZL5011X_DPLL_BASE + 0x0002c
#define ZL5011X_DPLL_CHK_MULTI_PERIOD_CNT ZL5011X_DPLL_BASE + 0x00030
#define ZL5011X_DPLL_CHK_MULTI_PERIOD_HIGH ZL5011X_DPLL_BASE + 0x00034
#define ZL5011X_DPLL_CHK_MULTI_PERIOD_LOW ZL5011X_DPLL_BASE + 0x00038
#define ZL5011X_DPLL_CHK_SIZE ((ZL5011X_DPLL_CHK_MULTI_PERIOD_LOW) - (ZL5011X_DPLL_CHK_SINGLE_PERIOD) + 4)
/* defines for bit fields in the DPLL registers */
/* ZL5011X_DPLL_CONTROL register bit positions */
#define ZL5011X_DPLL_REF_SPEED_BITS 7
#define ZL5011X_DPLL_POWERDOWN_BIT 6
#define ZL5011X_DPLL_BACKPLANE_SPEED_BIT 5
#define ZL5011X_DPLL_CLOCK_ALIGNMENT_BIT 4
#define ZL5011X_DPLL_FRAME_POLARITY_BIT 3
#define ZL5011X_DPLL_FRAME_ALIGNMENT_BIT 2
#define ZL5011X_DPLL_FRAME_WIDTH_BITS 0
#define ZL5011X_DPLL_REF_SPEED_MASK (Uint32T)0x7
#define ZL5011X_DPLL_FRAME_WIDTH_MASK (Uint32T)0x3
/* ZL5011X_DPLL_CENTRE_FREQ register bit positions */
#define ZL5011X_DPLL_CENTRE_FREQ_BITS 0
#define ZL5011X_DPLL_CENTRE_FREQ_MASK (Uint32T)0x3ffffff
#define ZL5011X_DPLL_MAX_INVERSE_VALUE (Uint32T)(1 << 31)
/* ZL5011X_DPLL_INVERSE_CENTRE_FREQ register bit positions */
#define ZL5011X_DPLL_INVERSE_CENTRE_BITS 0
#define ZL5011X_DPLL_INVERSE_CENTRE_MASK (Uint32T)0xff
/* ZL5011X_DPLL_INVERSE_T1_FREQ register bit positions */
#define ZL5011X_DPLL_INVERSE_T1_BITS 0
#define ZL5011X_DPLL_INVERSE_T1_MASK (Uint32T)0xff
#define ZL5011X_DPLL_INVERSE_T1_DIV 772
#define ZL5011X_DPLL_INVERSE_T1_MULT 1024
/* ZL5011X_DPLL_INVERSE_J2_FREQ register bit positions */
#define ZL5011X_DPLL_INVERSE_J2_BITS 0
#define ZL5011X_DPLL_INVERSE_J2_MASK (Uint32T)0xff
#define ZL5011X_DPLL_INVERSE_J2_DIV 789
#define ZL5011X_DPLL_INVERSE_J2_MULT 1024
/* ZL5011X_DPLL_LOCK_DETECT register bit positions */
#define ZL5011X_DPLL_LOCK_TIME_BITS 16
#define ZL5011X_DPLL_LOCK_THRESHOLD_BITS 0
#define ZL5011X_DPLL_LOCK_TIME_MASK (Uint32T)0xffff
#define ZL5011X_DPLL_LOCK_THRESHOLD_MASK (Uint32T)0xffff
/* ZL5011X_DPLL_LOCK_RANGE register bit positions */
#define ZL5011X_DPLL_LOCK_RANGE_BITS 0
#define ZL5011X_DPLL_LOCK_RANGE_MASK (Uint32T)0x3fff
/* ZL5011X_DPLL_SLEW_RATE register bit positions */
#define ZL5011X_DPLL_BANDWIDTH_CTRL_BITS 13
#define ZL5011X_DPLL_SLEW_RATE_BITS 0
#define ZL5011X_DPLL_BANDWIDTH_CTRL_MASK (Uint32T)0x7
#define ZL5011X_DPLL_SLEW_RATE_MASK (Uint32T)0x1fff
/* ZL5011X_DPLL_CHANGE_CONTROL register bit positions */
#define ZL5011X_DPLL_MTIE_ROUND_OFF_BITS 16
#define ZL5011X_DPLL_MTIE_RESET_BIT 5
#define ZL5011X_DPLL_REF_PRIORITY_BITS 2
#define ZL5011X_DPLL_FORCE_MODE_BITS 0
#define ZL5011X_DPLL_MTIE_ROUND_OFF_MASK (Uint32T)0xffff
#define ZL5011X_DPLL_REF_PRIORITY_MASK (Uint32T)0x7
#define ZL5011X_DPLL_FORCE_MODE_MASK (Uint32T)0x3
/* ZL5011X_DPLL_CHANGE_STATUS register bit positions */
/* moved to zl5011xPac.h */
/* ZL5011X_DPLL_CHK_SINGLE_PERIOD register bit positions */
#define ZL5011X_DPLL_CHK_SINGLE_HIGH_BITS 16
#define ZL5011X_DPLL_CHK_SINGLE_LOW_BITS 0
#define ZL5011X_DPLL_CHK_SINGLE_HIGH_MASK (Uint32T)0xffff
#define ZL5011X_DPLL_CHK_SINGLE_LOW_MASK (Uint32T)0xffff
/* ZL5011X_DPLL_CHK_MULTI_PERIOD_CNT register bit positions */
#define ZL5011X_DPLL_CHK_CNT_BITS 0
#define ZL5011X_DPLL_CHK_CNT_MASK (Uint32T)0xff
/* ZL5011X_DPLL_CHK_MULTI_PERIOD_HIGH register bit positions */
#define ZL5011X_DPLL_CHK_HIGH_BITS 0
#define ZL5011X_DPLL_CHK_HIGH_MASK (Uint32T)0xffffff
/* ZL5011X_DPLL_CHK_MULTI_PERIOD_LOW register bit positions */
#define ZL5011X_DPLL_CHK_LOW_BITS 0
#define ZL5011X_DPLL_CHK_LOW_MASK (Uint32T)0xffffff
/******************************************************************************
* PAC definitions
******************************************************************************/
/* addresses of registers for the PAC block */
#define ZL5011X_PAC_SETUP ZL5011X_PAC_BASE + 0x00004
#define ZL5011X_PAC_INTERRUPT_STATUS ZL5011X_PAC_BASE + 0x0024c
#define ZL5011X_PAC_INTERRUPT_MASK ZL5011X_PAC_BASE + 0x00250
#define ZL5011X_PAC_INTERRUPT_CLEAR ZL5011X_PAC_BASE + 0x00254
#define ZL5011X_PAC_PRIMARY_REF_CONTROL ZL5011X_PAC_BASE + 0x00400
#define ZL5011X_PAC_SECONDARY_REF_CONTROL ZL5011X_PAC_BASE + 0x00404
#define ZL5011X_PAC_WAN_FRAME_LENGTH ZL5011X_PAC_BASE + 0x00408
#define ZL5011X_PAC_PRS_TO_RTP_DIVIDER ZL5011X_PAC_BASE + 0x0040c
#define ZL5011X_PAC_DCO_INVERSE_FREQ ZL5011X_PAC_BASE + 0x00540
#define ZL5011X_PAC_TDL_AVG_CONTROL ZL5011X_PAC_BASE + 0x00548
#define ZL5011X_PAC_ASYNC_SETUP ZL5011X_PAC_BASE + 0x01000
#define ZL5011X_PAC_WAN_RX_BIT_COUNT ZL5011X_PAC_BASE + 0x01200
#define ZL5011X_PAC_DCO_FREQUENCY ZL5011X_PAC_BASE + 0x01600
#define ZL5011X_PAC_PTT_SETUP ZL5011X_PAC_BASE + 0x01a00
#define ZL5011X_PAC_JITTER_BASE ZL5011X_PAC_BASE + 0x01e00
#define ZL5011X_PAC_DATA_TTP_BASE ZL5011X_PAC_BASE + 0x02000
#define ZL5011X_PAC_DATA_PTT_BASE ZL5011X_PAC_BASE + 0x02200
#define ZL5011X_PAC_DATA_BIN_BASE ZL5011X_PAC_BASE + 0x03000
/* defines for bit fields in the PAC registers */
#define ZL5011X_PAC_NUMBER_FAST_DCO 2
/* ZL5011X_PAC_SETUP register bit positions */
#define ZL5011X_PAC_LIU_MODE_BITS 16
#define ZL5011X_PAC_DCO_DIVIDE_BITS 4
#define ZL5011X_PAC_PRS_RATE_BITS 0
#define ZL5011X_PAC_LIU_MODE_MASK (Uint32T)0x7
#define ZL5011X_PAC_DCO_DIVIDE_MASK (Uint32T)0x7
#define ZL5011X_PAC_PRS_RATE_MASK (Uint32T)0x7
#define ZL5011X_PAC_DPLL_CONFIG_BITS 12
#define ZL5011X_PAC_DPLL_CONFIG_MASK (Uint32T)0x3
#define ZL5011X_PAC_DPLL_OUTPUT_ENABLE (Uint32T)0x3
#define ZL5011X_PAC_LIU_T1_MODE (Uint32T)0x0
#define ZL5011X_PAC_LIU_E1_MODE (Uint32T)0x1
#define ZL5011X_PAC_LIU_J2_MODE (Uint32T)0x2
#define ZL5011X_PAC_LIU_E3_MODE (Uint32T)0x3
#define ZL5011X_PAC_LIU_DS3_MODE (Uint32T)0x4
/* PAC interrupt register bit positions */
/* the bits are defined in zl5011xPac.h, since they are used in the
application */
#define ZL5011X_PAC_INT_MASK (Uint32T)0x3000f
#define ZL5011X_DPLL_REF_LIMITS_MASK (Uint32T)0xf
#define ZL5011X_DPLL_PRIMARY_REF_LIMITS_BITS 4
#define ZL5011X_DPLL_SECONDARY_REF_LIMITS_BITS 8
/* ZL5011X_PAC_PRIMARY_REF_CONTROL &
ZL5011X_PAC_SECONDARY_REF_CONTROL registers bit positions */
#define ZL5011X_PAC_REF_SOURCE_BITS 16
#define ZL5011X_PAC_REF_DIVIDE_BITS 0
#define ZL5011X_PAC_REF_CONTROL_MASK (Uint32T)0x3f
#define ZL5011X_PAC_REF_DIVIDE_MASK (Uint32T)0x1fff
#define ZL5011X_PAC_PRIMARY_REF_SOURCE (Uint32T)62
#define ZL5011X_PAC_SECONDARY_REF_SOURCE (Uint32T)63
/* ZL5011X_PAC_WAN_FRAME_LENGTH register bit positions */
#define ZL5011X_PAC_FRAME_LENGTH_BITS 0
#define ZL5011X_PAC_FRAME_LENGTH_MASK (Uint32T)0x1fff
/* ZL5011X_PAC_PRS_TO_RTP_DIVIDER register bit positions */
#define ZL5011X_PAC_PRS_DIVIDER_BITS 0
#define ZL5011X_PAC_PRS_DIVIDER_MASK (Uint32T)0x1fff
#define ZL5011X_PAC_PRS_TO_RTP_MAX_HZ (Uint32T)35000000
/* ZL5011X_PAC_DCO_INVERSE_FREQ register bit positions */
#define ZL5011X_PAC_DCO_MAX_INVERSE_BITS 0
#define ZL5011X_PAC_DCO_MAX_INVERSE_MASK (Uint32T)0xff
#define ZL5011X_PAC_DCO_MAX_INVERSE_VALUE (Uint32T)(1 << 31)
#define ZL5011X_PAC_DCO_INVERSE_DIV (Uint32T)128
/* ZL5011X_PAC_TDL_AVG_CONTROL register bit positions */
#define ZL5011X_PAC_TDL_AVG_ENABLE_BIT 4
#define ZL5011X_PAC_TDL_AVG_BITS 0
#define ZL5011X_PAC_TDL_AVG_MASK (Uint32T)0x7
/* ZL5011X_PAC_ASYNC_SETUP register bit positions */
#define ZL5011X_PAC_ASYNC_SETUP_SIZE sizeof(Uint32T)
#define ZL5011X_PAC_PAYLOAD_FRAMES_BITS 8
#define ZL5011X_PAC_RTP_RATE_BITS 6
#define ZL5011X_PAC_RTP_ENABLE_BIT 5
#define ZL5011X_PAC_PRS_COUNT_ENABLE_BIT 4
#define ZL5011X_PAC_ASYNC_CLOCK_SRC_BIT 2
#define ZL5011X_PAC_ASYNC_DATA_MODE_BITS 0
#define ZL5011X_PAC_PAYLOAD_FRAMES_MASK (Uint32T)0x3f
#define ZL5011X_PAC_RTP_RATE_MASK (Uint32T)0x3
#define ZL5011X_PAC_ASYNC_DATA_MODE_MASK (Uint32T)0x3
#define ZL5011X_PAC_ASYNC_DATA_DIFF_MODE 0
#define ZL5011X_PAC_ASYNC_DATA_TRANSIT_MODE 1
/* ZL5011X_PAC_DCO_FREQUENCY register bit positions */
#define ZL5011X_PAC_DCO_FREQUENCY_SIZE sizeof(Uint32T)
#define ZL5011X_PAC_DCO_FREQUENCY_MASK (Uint32T)0xffffffff
#define ZL5011X_PAC_DCO_FREQUENCY_BITS 0
/* ZL5011X_PAC_PTT_SETUP register bit positions */
#define ZL5011X_PAC_PTT_SETUP_SIZE sizeof(Uint32T)
#define ZL5011X_PAC_AVERAGE_MODE_BITS 12
#define ZL5011X_PAC_MULT_ENABLE_BIT 9
#define ZL5011X_PAC_NO_LATE_PACKETS_BIT 2
#define ZL5011X_PAC_SHORT_TIMESTAMP_BIT 1
#define ZL5011X_PAC_SHORT_SEQUENCE_BIT 0
#define ZL5011X_PAC_AVERAGE_MODE_MASK (Uint32T)0xF
/* ZL5011X_PAC_JITTER_BASE register bit positions */
#define ZL5011X_PAC_JITTER_BASE_SIZE sizeof(Uint32T)
#define ZL5011X_PAC_JITTER_VALUE_BITS 4
#define ZL5011X_PAC_JITTER_FRACT_BITS 0
#define ZL5011X_PAC_JITTER_VALUE_MASK (Uint32T)0xFFFFF
#define ZL5011X_PAC_JITTER_FRACT_MASK (Uint32T)0xF
/* ZL5011X_PAC_DATA_PTT_BASE register bit positions */
#define ZL5011X_PAC_TX_DIFF_COUNT_BITS 0
#define ZL5011X_PAC_TX_SEQ_NUM_BITS 30
/* or */
#define ZL5011X_PAC_TRANSIT_INTEGER_BITS 16
#define ZL5011X_PAC_TX_DIFF_COUNT_MASK (Uint32T)0x3FFFFFFF
#define ZL5011X_PAC_TX_SEQ_NUM_MASK (Uint32T)0xC0000000
/* ZL5011X_PAC_DATA_TTP_BASE register bit positions */
#define ZL5011X_PAC_RX_DIFF_COUNT_BITS 0
#define ZL5011X_PAC_RX_SEQ_NUM_BITS 30
#define ZL5011X_PAC_RX_DIFF_COUNT_MASK (Uint32T)0x3FFFFFFF
#define ZL5011X_PAC_RX_SEQ_NUM_MASK (Uint32T)0xC0000000
/* ZL5011X_PAC_DATA_BIN_BASE register bit positions */
#define ZL5011X_PAC_DATA_BIN_SIZE (8 * sizeof(Uint32T))
#define ZL5011X_PAC_IN_BAND_DIFF_BITS 16
#define ZL5011X_PAC_IN_BAND_SEQ_NUM_BITS 0
#define ZL5011X_PAC_IN_BAND_DIFF_MASK (Uint32T)0xFFFF
#define ZL5011X_PAC_IN_BAND_SEQ_NUM_MASK (Uint32T)0xFFFF
#ifdef __cplusplus
}
#endif
#endif
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