📄 le1vefpgadma.h
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/* le1veFpgaDma.c - LE1VE DMA (FPGA) controller head file
*
* Copyright 2004-2007 ZTE, Inc.
* author: ZhengQishan
* date: 2004.02
*
* modification history
*------------------------------
*
*/
#ifndef _LE1VE_FPGA_DMA_H
#define _LE1VE_FPGA_DMA_H
#include "le1veLib.h"
#define LE1VE_DEVICE_ID 0x4F43
#define LE1VE_VENDOR_ID 0X10EE
/*控制收发描述符按2,4,8,16,32,...方式增加,便于发送描述队列的处理*/
#define DMA_DES_RING_SIZE 5
#define MAX_DMA_CHANNELS 2
#define SIZE_PER_DMA_BUF 2048 /*byte*/
#define LE1VE_MTU 1518
#define IXP1200_RX_DMA 0
#define IXP1200_TX_DMA 1
#define LE1VE_PCI_MAX_NUM 8
#define PCI_MEM_BASE_OFFSET 0x10 /*定义内存基地址在PCI配置空间中的偏移量*/
#define SLOT_DEVNO_BASE 15 /*定义与槽位相对应的基(加槽位号等于设备号*/
#define PCI_MEM_BASE_MASK 0xfffffff0 /*定义PCI内存基地址mask*/
#define PCI_CFG_COMMAND_OFFSET 0x04 /*定义PCI配置空间命令偏移量*/
#define PCI_CFG_CMD_MEM_ENABLE 0x0002 /* memory access enable */
#define PCI_CFG_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
/*PCI内存空间控制寄存器地址分配*/
#define RX_DESC_BASE_REG 0x00 /*上行BD表起始地址*/
#define TX_DESC_BASE_REG 0x04 /*下行BD表起始地址*/
#define DESC_NUM_REG 0x08 /*BD表条目*/
#define PCI_INT_REG 0x10 /*PCI中断寄存器*/
#define PCI_INT_MASK_REG 0x14 /*PCI中断掩码寄存器*/
#define TX_ENABLE_REG 0x20 /*下行启动收包寄存器 */
#define RX_ENABLE_REG 0x24 /*上行启动收包寄存器*/
/* MII接口寄存器地址( 0x1430 ~ 0x143C)*/
#define LE1VE_MII_INT_STAT_REG 0x1430
#define LE1VE_MII_INT_MASK_REG 0x1434
#define LE1VE_MII_CONTROL_REG 0x1438
#define LE1VE_MII_STATE_REG 0x143c
#define LE1VE_CTRL_PORT_RESET 0x01
#define LE1VE_CTRL_TX_ENABLE 0x04
#define LE1VE_CTRL_RX_ENABLE 0x08
#define LE1VE_CTRL_FULL_DUPLEX 0x10
#define LE1VE_CTRL_PREAM_ENABLE 0x20
#define LE1VE_CTRL_LOOP_BACK 0x40
#define LE1VE_CTRL_CRC_ENABLE 0x80
/*PCI接口CPU空间控制寄存器地址分配*/
#define LE1VE_PCI_CONTROL_REG 0x1440
#define LE1VE_LITTLE_ENDIAN 0
#define LE1VE_BIG_ENDIAN 0x01
/*FPGA内部计数地址分配*/
#define LE1VE_COUNT_CONTROL_REG 0X1444
#define LE1VE_MII_RX_CNT_REG 0x1450
#define LE1VE_MII_RX_ERR_CNT_REG 0x1460
#define LE1VE_MII_TX_CNT_REG 0x1470
#define LE1VE_MII_TX_ERR_CNT_REG 0x1480
#define LE1VE_PCI_RX_CNT_REG 0x1490
#define LE1VE_PCI_RX_ERR_CNT_REG 0x14A0
#define LE1VE_PCI_TX_CNT_REG 0x14B0
#define LE1VE_PCI_TX_ERR_CNT_REG 0x14C0
#define RMD0_OWN 0x80000000 /* Own */
#define RMD0_ERR 0x40000000 /* Error */
#define RMD0_PKT_LEN 0x0000ffff /*packet length*/
/* transmit descriptor */
#define TMD0_CLEAR 0x00000000 /*clear*/
#define TMD0_OWN 0x80000000 /* Own */
#define TMD0_ERR 0x40000000 /* Error */
#define TMD0_PKT_LEN 0x0000ffff /*packet length*/
/*PCI中断状态*/
#define LE1VE_TX_BD_OPT_ERR_INT 0x01
#define LE1VE_RX_BD_FULL_INT 0x02
#define LE1VE_RX_PKT_INT 0x08
#define LE1VE_TX_TRANS_ERR_INT 0x10
#define LE1VE_RX_TRANS_ERR_INT 0x20
#define LE1VE_INT_ALL_MASK 0xFFFFFFC4
/*Rx and Tx Control*/
#define LE1VE_RX_BD_FULL 0x01
#define DEV_LE1VE_PCI_QLEN 64
#define LE1VE_RX_PKT_ENABLE 0x01
#define LE1VE_TX_PKT_ENABLE 0x01
typedef struct Le1ve_RMD
{
volatile UINT32 RMD0; /*bit31:own bit30:ERR bit29-16:reversed bit15-0:packet_length*/
volatile UINT32 RMD1; /* bits 31:00 of receive buffer address */
} LE1VE_RMD;
/* Transmit Message Descriptor Entry. */
typedef struct le1ve_TMD
{
volatile UINT32 TMD0; /*bit31:own bit30:ERR bit29-16:reversed bit15-0:packet_length*/
volatile UINT32 TMD1; /* bits 31:00 of transmit buffer address */
} LE1VE_TMD;
typedef struct
{
volatile unsigned long rxDescBase; /*0x00 上行BD表起始地址*/
volatile unsigned long txDescBase; /*0x04 下行BD表起始地址*/
volatile unsigned long descNum; /*0x08 BD表条目*/
volatile unsigned long reserved1; /*0x0C reserved*/
volatile unsigned long pciIntState; /*0x10 PCI中断寄存器*/
volatile unsigned long pciIntMask; /*0x14 PCI中断掩码寄存器*/
volatile unsigned long reserved2; /*0x18 reserved*/
volatile unsigned long reserved3; /*0x1C reserved*/
volatile unsigned long txEnable; /*0x20 下行启动收包寄存器 */
volatile unsigned long rxEnable; /*0x24 上行启动收包寄存器*/
}LE1VE_PCI_MEM_MAP;
typedef enum
{
NO_CLEAR_TO_ZERO = 0,
CLEAR_TO_ZERO
}LE1VE_FPGA_CNT_CTRL_MODE;
typedef enum
{
RX_PKT_JOB_NOT_ADDED = 0,
RX_PKT_JOB_ADDED =1
}LE1VE_RX_PKT_JOB_STATE;
typedef struct
{
int mode;
unsigned int MiiRxCnt;
unsigned int MiiRxErrCnt;
unsigned int MiiTxCnt;
unsigned int MiiTxErrCnt;
unsigned int PciRxCnt;
unsigned int PciRxErrCnt;
unsigned int PciTxCnt;
unsigned int PciTxErrCnt;
}LE1VE_FPGA_DMA_STATIS;
typedef struct freeArgs
{
void * arg1;
void * arg2;
} FREE_ARGS;
typedef struct le1veDevice
{
/*PCI属性*/
int deviceId;
int vendorId;
int busNo;
int devNo;
int functionNo;
void *pNet;
SEM_ID TxSemaphore;
int uintNo; /* unit number of the device */
int slotNo; /*slot No of the device*/
LE1VE_PCI_MEM_MAP *pMem; /* memory base as seen from PCI*/
UINT32 cpuMemBase; /* memory base as seen from CPU*/
int rmdIndex; /* current RMD index */
int rringSize; /* RMD ring size */
int rringLen; /* RMD ring length (bytes) */
LE1VE_RMD *pRring; /* RMD ring start */
int tmdIndex; /* current TMD index */
int tmdIndexC; /* current take back TMD index */
int tringSize; /* TMD ring size */
int tringLen; /* TMD ring length (bytes) */
LE1VE_TMD *pTring; /* TMD ring start */
char * pShMem; /* real ptr to shared memory */
char * memBase; /* LANCE memory pool base */
UINT32 flags; /* Our local flags */
BOOL txBlocked; /* transmit flow control */
BOOL txCleaning; /* transmit descriptor cleaning */
FREE_ARGS freeData [128]; /* Array of free arguments */
int rxFlag; /*接收任务处理标志,如果当前已经有任务处理,此标志置1,否则为0*/
unsigned int le1vePciResetInt;
unsigned int le1vePciInt;
unsigned int le1veRxInt; /**收包中断**/
unsigned int le1vePciTxInt; /**发包中断**/
unsigned int le1vePciRxFullInt; /*上行BD表满中断*/
unsigned int le1vePciTxEmptyInt; /*下行BD表空中断*/
unsigned int le1vePciTxMemErr; /*下行memory读写错误*/
unsigned int le1vePciRxMemErr; /*上行memory读写错误*/
unsigned int le1vepciRx; /* 收包计数 */
unsigned int le1vepciTx; /* 发包计数*/
unsigned int le1vePciTxNoTmd; /*发送无描述符*/
unsigned int le1vePciRxErrorPkt; /*收到错误包*/
unsigned int le1veErrorAddJob;
unsigned int le1veErrorAlloc;
unsigned int le1vePciFpgaMode;
unsigned int le1vePciAddJob;
unsigned char pciOnline;
} LE1VE_PCI_DRV_CTRL;
#define CHECK_CNT_CTRL_MODE(mode)\
do{\
if(((mode) != NO_CLEAR_TO_ZERO) && ((mode) != CLEAR_TO_ZERO))\
return ERROR;\
}while(0);
#define READ_CNT_REG(reg) \
(Drv_Swap32(*((volatile UINT32 *)(reg))) & 0xFF) |\
((Drv_Swap32(*((volatile UINT32 *)(reg + 4))) << 8) & 0xFF00) | \
((Drv_Swap32(*((volatile UINT32 *)(reg + 8))) << 16) & 0xFF0000) | \
((Drv_Swap32(*((volatile UINT32 *)(reg + 0x0c))) << 24) & 0xFF000000)\
#define LE1VE_CLEAN_RXD(rmd) \
{ \
rmd->RMD0 = 0; \
}
#define LE1VE_TMD_CLR_ERR(tmd) \
{ \
tmd->TMD0 = 0; \
tmd->TMD1 = 0; \
}
#define LE1VE_MII_CTRL_WR(pDrv, reg, value)\
*((volatile UINT32 *)(pDrv->cpuMemBase + reg)) = Drv_Swap32(value);
#define LE1VE_MII_CTRL_RD(pDrv, reg, value)\
*(value) = Drv_Swap32(*((volatile UINT32 *)(pDrv->cpuMemBase + reg)));
#endif /*_LE1VE_FPGA_DMA_H*/
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