le1vefpgalib.h

Zalink50114----TDMoIP芯片驱动源码

/* le1veFPGALib.h - LE1VE(TDMoIP) card FPGA header file
*
* Copyright     2004-2007 ZTE, Inc.
* author:       ZhengQishan
* date:         2004.02
*
* modification history
*------------------------------
*
*/

#ifndef _FPGA_LIB_H
#define _FPGA_LIB_H
#ifdef __cplusplus
extern "C" {
#endif
#include  "le1veLib.h"

/*CPU访问寄存器地址*/
#define   FPGA_VERSION_REG     		0x1400
#define   FPGA_DEVICEID_REG			0x1404
#define   FPGA_DOWNLOAD_FLAG_LOW	0x1408   /*0x55*/
#define   FPGA_DOWNLOAD_FLAG_HIGH	0x140C   /*0xAA*/
#define   FPGA_CONTROL_REG			0x1410
#define   FPGA_ADDR_REG0			0x1414
#define   FPGA_ADDR_REG1			0x1418
#define   FPGA_ADDR_REG2			0x141c
#define   FPGA_DATA_REG0			0x1420
#define   FPGA_DATA_REG1			0x1424
#define   FPGA_DATA_REG2			0x1428
#define   FPGA_DATA_REG3			0x142c

/*MII接口寄存器地址分配*/
#define   FPGA_MII_INT_STATUS_REG	0x1430
#define   FPGA_MII_INT_CRTL_REG		0x1434
#define   FPGA_MII_PORT_CRTL_REG	0x1438
#define   FPGA_MII_PORT_STATUS_REG	0X143C

/*CPU访问控制寄存器*/
#define   FPGA_CTRL_WRI_ENABLE		0x01
#define   FPGA_CTRL_RD_ENABLE		0x02
#define   FPGA_CTRL_RD_WR_TIMEOUT   0x20
#define   FPGA_CTRL_RD_READY		0X40
#define   FPGA_CTRL_WR_BUSY			0x80

/*中断控制寄存器*/
#define   FPGA_MII_LINK_CHANGE_INT_ENABLE			0x01
#define   FPGA_MII_PORT_OPTION_CHANGE_INT_ENABLE 	0x02

/*中断状态寄存器*/
#define   FPGA_MII_LINK_CHANGE_INT_STATUS			0x01
#define   FPGA_MII_PORT_OPTION_CHANGE_INT_STATUS 	0x02

/*端口控制寄存器*/
#define   FPGA_MII_PORT_RESET			0x01
#define   FPGA_MII_PORT_TX_ENABLE		0x04
#define   FPGA_MII_PORT_RX_ENABLE		0x08
#define   FPGA_MII_PORT_FULL_DUPLEX 	0x10
#define   FPAG_MII_PREAMBLE_ENABLE      0x20
#define   FPGA_MII_LOOPBACK_ENABLE		0x40

/*MII接口状态寄存器*/
#define   FPGA_MII_100BASE_TMODE		0x01
#define   FPGA_MII_TX_OK				0x02
#define   FPGA_MII_RX_OK				0x04

#define   FPGA_WR_RD_TIMEOUT            3     /*ticks*/

extern void ZL5011X_REG_WRITE(int slot, UINT32 reg, UINT32 value);
extern void ZL5011X_REG_READ(int slot, UINT32 reg, volatile UINT32 *value);


#ifdef __cplusplus
}
#endif

#endif /*_FPGA_LIB_H*/