zl5011xtmmap.h

Zalink50114----TDMoIP芯片驱动源码

/*******************************************************************************
*
*  File name:              zl5011xTmMap.h
*
*  Version:                6
*
*  Author:                 MRC
*
*  Date created:           09/04/2002
*
*  Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
*  All rights reserved.
*
*  Module Description:
*
*  This is the register definitions header file for TM block.
*  It contains the register offsets and bit field definitions.
*
*  Revision History:
*
*  Rev:  Date:       Author:  Comments:
*  1     09/04/2002  MRC      Creation
*  2     16/04/2002  MRC      Minor mods
*  3     10/06/2002  LCW      Minor mods
*  4     10/07/2002  MRC      Changed the queue sizes in the TM.
*  5     24/07/2002  MRC      Updated the bit positions for the Trace buffer.
*  6     31/10/2002  MRC      Added variants + minor fixes
*
*******************************************************************************/

#ifndef _ZL5011X_TM_MAP_H
#define _ZL5011X_TM_MAP_H

#ifdef __cplusplus
extern "C" {
#endif

/* addresses for the TM registers */
#define ZL5011X_TM_CONTROL               ZL5011X_TM_BASE + 0x00000

/* the input ports have several registers. The base address for each of
   these register banks is as follows */
#define ZL5011X_TM_PORT0_BASE            ZL5011X_TM_BASE + 0x00000
#define ZL5011X_TM_PORT1_BASE            ZL5011X_TM_BASE + 0x00080
#define ZL5011X_TM_PORT2_BASE            ZL5011X_TM_BASE + 0x00100
#define ZL5011X_TM_PORT3_BASE            ZL5011X_TM_BASE + 0x00180

#define ZL5011X_TM_PORT_REG_SIZE         (ZL5011X_TM_PORT1_BASE - ZL5011X_TM_PORT0_BASE)

/* the offsets for the various input port registers is as follows */
#define ZL5011X_TM_STATUS_OFFSET         0x00008
#define ZL5011X_TM_SEG_ADDRESS_OFFSET    0x0000c
#define ZL5011X_TM_SEG_SPACE_OFFSET      0x0002c

#define ZL5011X_TM_TRACE_POINTER         ZL5011X_TM_BASE + 0x00040
#define ZL5011X_TM_INTERRUPT_CLEAR       ZL5011X_TM_BASE + 0x00044
#define ZL5011X_TM_INTERRUPT_MASK        ZL5011X_TM_BASE + 0x00084
#define ZL5011X_TM_INTERRUPT_STATUS      ZL5011X_TM_BASE + 0x000c0
#define ZL5011X_TM_LOOKUP_RAM            ZL5011X_TM_BASE + 0x04000
#define ZL5011X_TM_LOOKUP_RAM_CPU        ZL5011X_TM_LOOKUP_RAM + 0x00000
#define ZL5011X_TM_LOOKUP_RAM_PLA        ZL5011X_TM_LOOKUP_RAM + 0x00100
#define ZL5011X_TM_LOOKUP_RAM_RTP        ZL5011X_TM_LOOKUP_RAM + 0x00200
#define ZL5011X_TM_LOOKUP_RAM_PKC        ZL5011X_TM_LOOKUP_RAM + 0x00300
#define ZL5011X_TM_TRACE_BUFFER          ZL5011X_TM_BASE + 0x05000

#define ZL5011X_TM_TRACE_BUFFER_SIZE     (Uint32T)1024

/* defines for bit fields in the registers */

/* control register ZL5011X_TM_CONTROL bit positions */
#define ZL5011X_TM_TRACE_TIMER_BIT          19
#define ZL5011X_TM_TRACE_MODE_BITS          17
#define ZL5011X_TM_TRACE_ENABLE_BIT         16
#define ZL5011X_TM_LOOKUP_RAM_ENABLE_BITS   0

#define ZL5011X_TM_TRACE_MODE_MASK          (Uint32T)0x3

/* Lookup RAM registers bit positions */
#define ZL5011X_TM_LOOKUP_RAM_BITS          0

#define ZL5011X_TM_LOOKUP_RAM_MASK          (Uint32T)0xf

#define ZL5011X_TM_NUM_LOOKUP_RAM_ENTRIES   (Uint32T)32
#define ZL5011X_TM_LOOKUP_RAM_SIZE          sizeof(Uint32T)

/* Input buffer address registers bit positions */
#define ZL5011X_TM_INPUT_SEG_END_BITS       16
#define ZL5011X_TM_INPUT_SEG_START_BITS     0

#define ZL5011X_TM_INPUT_SEG_ADDRESS_MASK   (Uint32T)0x1ff

/* Input buffer space registers bit positions */
#define ZL5011X_TM_ODD_SEG_SPACE_BITS       16
#define ZL5011X_TM_EVEN_SEG_SPACE_BITS      0

#define ZL5011X_TM_SEG_SPACE_MASK           (Uint32T)0xff

/* bit positions for ZL5011X_TM_TRACE_POINTER register */
#define ZL5011X_TM_TRACE_POINTER_BITS       0
#define ZL5011X_TM_TRACE_POINTER_MASK       (Uint32T)0x2ff

#define ZL5011X_TM_SEG_SPACE_MASK           (Uint32T)0xff

/* definitions for the input port queues */
#define ZL5011X_TM_PORT_MAX_QUEUE_SIZE      (Uint32T)63
#define ZL5011X_TM_PORT_MIN_QUEUE_SIZE      (Uint32T)1
#define ZL5011X_TM_PORT_TOTAL_QUEUE_SIZE    (Uint32T)127
#define ZL5011X_TM_MESSAGE_SIZE_WORDS       (Uint32T)4

/* default settings for the segment sizes for the input ports */
/* CPU input port */
#define ZL5011X_TM_CPU_PORT_CPU_DEFAULT     (Uint32T)4
#define ZL5011X_TM_CPU_PORT_TFQ_DEFAULT     (Uint32T)60
#define ZL5011X_TM_CPU_PORT_RTP_DEFAULT     (Uint32T)3
#define ZL5011X_TM_CPU_PORT_PKQ_DEFAULT     (Uint32T)60

/* PLA input port */
#define ZL5011X_TM_PLA_PORT_CPU_DEFAULT     (Uint32T)26
#define ZL5011X_TM_PLA_PORT_TFQ_DEFAULT     (Uint32T)1
#define ZL5011X_TM_PLA_PORT_RTP_DEFAULT     (Uint32T)50
#define ZL5011X_TM_PLA_PORT_PKQ_DEFAULT     (Uint32T)50

/* RTP input port */
#define ZL5011X_TM_RTP_PORT_CPU_DEFAULT     (Uint32T)62
#define ZL5011X_TM_RTP_PORT_TFQ_DEFAULT     (Uint32T)1
#define ZL5011X_TM_RTP_PORT_RTP_DEFAULT     (Uint32T)1
#define ZL5011X_TM_RTP_PORT_PKQ_DEFAULT     (Uint32T)63

/* PKC input port */
#define ZL5011X_TM_PKC_PORT_CPU_DEFAULT     (Uint32T)42
#define ZL5011X_TM_PKC_PORT_TFQ_DEFAULT     (Uint32T)63
#define ZL5011X_TM_PKC_PORT_RTP_DEFAULT     (Uint32T)1
#define ZL5011X_TM_PKC_PORT_PKQ_DEFAULT     (Uint32T)21

#ifdef __cplusplus
}
#endif

#endif