zl5011xpkimap.h

Zalink50114----TDMoIP芯片驱动源码

/*******************************************************************************
*
*  File name:              zl5011xPkiMap.h
*
*  Version:                7
*
*  Author:                 PJE
*
*  Date created:           16/04/2002
*
*  Copyright 2002, 2003, 2004, 2005, Zarlink Semiconductor Limited.
*  All rights reserved.
*
*  Module Description:
*
*  Revision History:
*
*  Rev:  Date:       Author:  Comments:
*  1     18/04/2002  PJE      Done easy bits - compile OK.
*  2     17/05/2002  PJE      tested most.
*  3     21/05/2002  PJE      tested rest.
*  4     05/06/2002  PJE      review items done.
*  5     06/06/2002  PJE      PKI review items tested.
*  6     25/10/2002  PJE      API tidy up
*  7     31/10/2002  MRC      Added variants + minor fixes
*
*******************************************************************************/

#ifndef _ZL5011X_PKI_MAP_H_
#define _ZL5011X_PKI_MAP_H_

#ifdef __cplusplus
extern "C" {
#endif

/*****************   # DEFINES   **********************************************/

/* addresses for the registers  */
#define ZL5011X_PKI0_CTRL  ZL5011X_PKI_BASE + 0x00000  /* PKI Port 0 Control Register */
#define ZL5011X_PKI0_ADR_LO   ZL5011X_PKI_BASE + 0x00010  /* PKI Port 0 Address bits 31 to 0 */
#define ZL5011X_PKI0_ADR_HI   ZL5011X_PKI_BASE + 0x00014  /* PKI Port 0 Address bits 47 to 32 */
#define ZL5011X_PKI0_FRAME_SIZE  ZL5011X_PKI_BASE + 0x00030  /* PKI Port 0 Frame Size Limitation; */
#define ZL5011X_VLAN_TYPE       ZL5011X_PKI_BASE + 0x00040   /* VLAN Type Register; */
#define ZL5011X_INT_MASK_WAS0    ZL5011X_PKI_BASE + 0x00044  /* Interrupt mask for
                                          statistic wrap around register port 0 */
#define ZL5011X_INT_MASK_PCS_DET ZL5011X_PKI_BASE + 0x00054  /*Interrupt mask for PCS mode
                                          carrier sense signal change register */
#define ZL5011X_MDIO_CPU_RDATA   ZL5011X_PKI_BASE + 0x00058  /*MDIO Command Register */
#define ZL5011X_WAS0_CPU_RDATA   ZL5011X_PKI_BASE + 0x0005C  /*Statistic Wrap Around
                                                         Register Port 0 */
#define ZL5011X_PCS_SIGNAL_DET   ZL5011X_PKI_BASE + 0x0006C  /*PCS mode carrier sense
                                                         signal change */
#define ZL5011X_PKI_RAM_BASE    ZL5011X_PKI_BASE + 0x4000 /* Start of Mac Stats Storage area */
#define ZL5011X_PKI_MAC_STATS_SIZE 0x20 /* Size of Mac Stats for one port
                                                      (=32 x 32bit registers) */

/* bit definitions in the Statistic Wrap Around Registers */
#define ZL5011X_WRAP_BYTESSENT     0
#define ZL5011X_WRAP_UNICASTSENT   1
#define ZL5011X_WRAP_SENDFAIL      2
#define ZL5011X_WRAP_FCSENT        3
#define ZL5011X_WRAP_NUCSENT       4
#define ZL5011X_WRAP_BYTESRECD     5
#define ZL5011X_WRAP_PKTSRECD      6
#define ZL5011X_WRAP_GOODBYTESRECD 7
#define ZL5011X_WRAP_FRAMESRECD    8
#define ZL5011X_WRAP_FCRECD        9
#define ZL5011X_WRAP_MCASTRECD     10
#define ZL5011X_WRAP_BCRECD        11
#define ZL5011X_WRAP_64            12
#define ZL5011X_WRAP_JABBER        13
#define ZL5011X_WRAP_65TO127       14
#define ZL5011X_WRAP_OVERSIZE      15
#define ZL5011X_WRAP_128TO255      16
#define ZL5011X_WRAP_256TO511      17
#define ZL5011X_WRAP_512TO1023     18
#define ZL5011X_WRAP_1023TO1518    19
#define ZL5011X_WRAP_FRAGMENT      20
#define ZL5011X_WRAP_ALIGNERR      21
#define ZL5011X_WRAP_UNDERSIZE     22
#define ZL5011X_WRAP_CRC           23
#define ZL5011X_WRAP_SHORTEVENT    24
#define ZL5011X_WRAP_COLLISION     25
#define ZL5011X_WRAP_DROPEVENT     26
#define ZL5011X_WRAP_FILTER        27
#define ZL5011X_WRAP_CTR_UNUSED    28
#define ZL5011X_WRAP_LATECOLLISION 29
#define ZL5011X_WRAP_ALL           (0x2FFFFFFF)
#define ZL5011X_PKI_MASK_SPECIFIED_64BIT  0x0000000A1 /* bytes sent b0 & bytes recd. b5 and
                                                         good bytes received b7*/

/* defines for bits in control registers */
#define ZL5011X_PKI_CTRL_REG_N_RESET           14
#define ZL5011X_PKI_CTRL_REG_TEST_SPDUP          13
#define ZL5011X_PKI_CTRL_REG_STA_RESET           12
#define ZL5011X_PKI_CTRL_REG_DISABLE_RESET_PCS   11
#define ZL5011X_PKI_CTRL_REG_PWD_SAVE_EN         10
#define ZL5011X_PKI_CTRL_REG_ILPBK               9
#define ZL5011X_PKI_CTRL_REG_ADDR_FILTER2        8
#define ZL5011X_PKI_CTRL_REG_ADDR_FILTER1        7
#define ZL5011X_PKI_CTRL_REG_ADDR_FILTER0        6
#define ZL5011X_PKI_CTRL_REG_LONG_PKT            5
#define ZL5011X_PKI_CTRL_REG_SEL_PCS             4
#define ZL5011X_PKI_CTRL_REG_SEL_MII             3
#define ZL5011X_PKI_CTRL_REG_VLAN_AWARE          2
#define ZL5011X_PKI_CTRL_REG_FDPLEX              1
#define ZL5011X_PKI_CTRL_REG_LINKDOWN            0

/* 21 bits for frame size registers */
#define ZL5011X_PKI_FRAMESIZE_MASK               0x1FFFFF

/* bit definitions for the MDIO Register */
#define ZL5011X_PKI_MDIO_RDY_MASK              0x80000000  /* Bit mask used to check
                           the condition of the RDY bit in the MDIO register */
#define ZL5011X_PKI_MDIO_RDY                   0x80000000
#define ZL5011X_PKI_MDIO_VALID_MASK            0x40000000  /* Bit mask used to check
                           the condition of the VALID bit in the MDIO register */
#define ZL5011X_PKI_MDIO_VALID                 0x40000000
#define ZL5011X_PKI_MDIO_DATA_MASK             0x0000FFFF  /* Bit mask used on the
                                          16 bit data read back from the phy */
#define ZL5011X_PKI_MDIO_PHY_READ_COMMAND      0x60000000  /* Initial framework for
                                                      the phy 'read' command */
#define ZL5011X_PKI_MDIO_PHY_WRITE_COMMAND     0x50000000  /* Initial framework for
                                                         the phy 'write' command */
#define ZL5011X_PKI_MDIO_TURN_AROUND           0x00020000  /* Bit mask to set the
                                       Turn Around bits in the MDIO register */
#define ZL5011X_PKI_MDIO_PHY_ADDRESS_SHIFT     23          /* Phy Address occupies
                                                bits 27:23 in the MDIO register */
#define ZL5011X_PKI_MDIO_PHY_REGISTER_SHIFT    18          /* Phy Register occupies
                                                bits 22:18 in the MDIO register */


/*****************   DATA TYPES   *********************************************/


/*****************   DATA STRUCTURES   ****************************************/

/*****************   EXPORTED GLOBAL VARIABLE DECLARATIONS   ******************/

#ifdef __cplusplus
}
#endif

#endif /* _ZL5011X_PKI_MAP_H_ */