f91_pll.s

zilog的实时操作系统RZK,可以移植到多种处理器上

;******************************************************************************
; Copyright 2004, ZiLOG Inc.																	*
; All Rights Reserved																			*
;																										*
; This is UNPUBLISHED PROPRIETARY SOURCE CODE of ZiLOG Inc., and might			*
; contain proprietary, confidential and trade secret information of				*
; ZiLOG, our partners and parties from which this code has been licensed.		*
;																										*
; The contents of this file may not be disclosed to third parties, copied or	*
; duplicated in any form, in whole or in part, without the prior written		*
; permission of ZiLOG Inc.																		*
;******************************************************************************
.if _EZ80F91

	.assume	adl=1

;	.def	_F91_PLL_Init

_F91_PLL_Init:
	;***	Configure PLL
	.extern _F91_PLL_config
;	.extern done_pll_init

	ld		hl, _F91_PLL_config

	;***  Select the Oscillator as the system clock
   in0   a, (PLL_CTL0)
   and   a, 0CCh
   out0  (PLL_CTL0), a

	;***	Disable the PLL
	in0	a, (PLL_CTL1)
	and	a, 0FEh
	out0	(PLL_CTL1), a

	;***	Set PLL Freq Divider
	ld		a, (hl)
	inc	hl
	out0	(PLL_DIV_L), a
	ld		a, (hl)
	inc	hl
	out0	(PLL_DIV_H), a

	;***	Program Control register 0 (except clock source)
	ld		a, (hl)
	inc	hl
	ld		e, a
	and	a, 0CCh
	out0	(PLL_CTL0), a

	;***	Stop if the PLL is not supposed to be enabled
	ld		a, (hl)
	tst   a, 001h
	jr		z, leave_pll_disabled
	out0	(PLL_CTL1), a
wait_for_lock:
	in0	a, (PLL_CTL1)
	and	a, 020h
	jr		z, wait_for_lock

	;***	Program final value of Control register 0
	out0	(PLL_CTL0), e

leave_pll_disabled:
;	jp		done_pll_init

.endif