boot_l92_iar.s

zilog的实时操作系统RZK,可以移植到多种处理器上

;********************************************************************************
; Copyright 2004, ZiLOG Inc.													*
; All Rights Reserved															*
;																				*
; This is UNPUBLISHED PROPRIETARY SOURCE CODE of ZiLOG Inc., and might			*
; contain proprietary, confidential and trade secret information of				*
; ZiLOG, our partners and parties from which this code has been licensed.		*
;																				*
; The contents of this file may not be disclosed to third parties, copied or	*
; duplicated in any form, in whole or in part, without the prior written		*
; permission of ZiLOG Inc.														*
;																				*
; Copyright 2001, Metro Link, Inc.												*
; All Rights Reserved															*
;																				*
; This is UNPUBLISHED PROPRIETARY SOURCE CODE of Metro Link, Inc. and may		*
; contain proprietary, confidential and trade secret information of				*
; Metro Link, Inc. and/or its partners.											*
;																				*
; The contents of this file may not be disclosed to third parties, copied or	*
; duplicated in any form, in whole or in part, without the prior written		*
; permission of Metro Link, Inc.												*
;********************************************************************************

;*******************************************************************************
;*                                                                             *
;* Module:		Boot_L92.asm                                                   *
;* Desciption:	Code to disable interrupts and/or disable all on-chip          *
;*             peripherals.                                                    *
;* Revision Log:                                                               *
;* Date		Who   What                                                         *
;* ------   ---   ----                                                         *
;* 031802   MCB   Created.                                                     *
;*******************************************************************************


	;***	Set the Bus Mode for external perihperals
	EXTERN cs_bus_mode
	ld		hl, cs_bus_mode
	ld		a, (hl)
	out0 	(CS0_BMC), a
	inc	hl
	ld		a, (hl)
	out0 	(CS1_BMC), a
	inc	hl
	ld		a, (hl)
	out0 	(CS2_BMC), a
	inc	hl
	ld		a, (hl)
	out0 	(CS3_BMC), a


	;***	Configure Chip Selects
	EXTERN cs_config

	;***	CS0
	ld		hl, cs_config
	ld		a, (hl)
	out0 	(CS0_LBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS0_UBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS0_CTL), a

	;***	CS1
	inc	hl
	ld		a, (hl)
	out0 	(CS1_LBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS1_UBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS1_CTL), a

	;***	CS2
	inc	hl
	ld		a, (hl)
	out0 	(CS2_LBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS2_UBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS2_CTL), a

	;***	CS3
	inc	hl
	ld		a, (hl)
	out0 	(CS3_LBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS3_UBR), a
	inc	hl
	ld		a, (hl)
	out0 	(CS3_CTL), a


	EXTERN GPIO_config
	ld		hl, GPIO_config

	;***	Port B GPIO
	ld		a, (hl)
	out0	(PB_DR), a
	inc	hl
	ld		a, (hl)
	out0	(PB_DDR), a
	inc	hl
	ld		a, (hl)
	out0	(PB_ALT1), a
	inc	hl
	ld		a, (hl)
	out0	(PB_ALT2), a
	inc	hl

	;***	Port C GPIO
	ld		a, (hl)
	out0	(PC_DR), a
	inc	hl
	ld		a, (hl)
	out0	(PC_DDR), a
	inc	hl
	ld		a, (hl)
	out0	(PC_ALT1), a
	inc	hl
	ld		a, (hl)
	out0	(PC_ALT2), a
	inc	hl

	;***	Port D GPIO
	ld		a, (hl)
	out0	(PD_DR), a
	inc	hl
	ld		a, (hl)
	out0	(PD_DDR), a
	inc	hl
	ld		a, (hl)
	out0	(PD_ALT1), a
	inc	hl
	ld		a, (hl)
	out0	(PD_ALT2), a
	inc	hl


	;****	Disable all PRTCs
	ld		a, 00h
	out0	(TMR0_CTL), a
	out0	(TMR1_CTL), a
	out0	(TMR2_CTL), a
	out0	(TMR3_CTL), a
	out0	(TMR4_CTL), a
	out0	(TMR5_CTL), a


	;***	Disable Watchdog timer
	out0	(WDT_CTL), a

	;***	Disable UART interrupts
	out0	(UART0_IER), a
	out0	(UART1_IER), a

	;***	Set PRTC0..3 input sources as System Clock / Prescaler.
	out0	(TMR_ISS),  a

	;***	Disable IR
	out0 	(IR_CTL), a

	;***	Disable I2C interrupts
	out0	(I2C_CTL), a

	;***	Apply system clock to all peripherals
	out0	(CLK_PPD1), a
	out0	(CLK_PPD2), a

	;***	Disable RTC interrupts
	in0	a, (RTC_CTRL)
	and   a, 0BFh
	out0	(RTC_CTRL), a

	;***	Disable SPI interrupts
	ld		a, 04
	out0	(SPI_CTL), a