mux.vhdl

来自「Direct Digital Synthesis (DDS),最好用的可步进的数」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux is
		port(mode:in std_logic_vector(1 downto 0);
			  sindata:in std_logic_vector(7 downto 0);
			  squadata: in std_logic_vector(7 downto 0);
			  tridata:in std_logic_vector(7 downto 0);
			  ddsdata:out std_logic_vector(7 downto 0)
			  );			  
end mux;

architecture Behavioral of mux is

begin
	process(mode,sindata,squadata,tridata)
	begin
		if mode="00" then 
			ddsdata<=sindata;
		elsif mode="01" then
			ddsdata<=squadata;
		elsif mode="10" then 
		   ddsdata<=tridata;
		else ddsdata<=sindata;
		end if;
	end process;

end Behavioral;