target.nr

vxworks bsp for pc pentium3 开发环境为tornado2.2 for pentium。

vxWorks.st	T{
A fully linked standalone vxWorks, including target based shell, symbol
table, and network interface.  The network interface is not initialized.
There is no WDB agent.
T}
vxWorks.res_rom	T{
A standalone VxWorks image that can be put in ROM.
Only the data segment of this ROM image is copied into RAM.
T}
vxWorks.res_rom_nosym	T{
A standalone VxWorks image that can be put in ROM.
Only the data segment of this ROM image is copied into RAM.
There is no symbol table. 
T}
_
.TE

.SS "Special Routines"
The following routines are specific to this BSP and are available
to the user. The are written in assembly code in sysALib.s. For 
further details see the reference entries:
.TS
expand;
sysInByte() | input one byte from I/O space
sysInWord() | input one word from I/O space
sysInLong() | input one long-word from I/O space
sysOutByte() | output one byte to I/O space
sysOutWord() | output one word to I/O space
sysOutLong() | output one long-word to I/O space
sysInWordString() | input word string from I/O space
sysInLongString() | input long string from I/O space
sysOutWordString() | output word string to I/O space
sysOutLongString() | output long string to I/O space
.TE


.SH "KNOWN PROBLEMS"

.SS "Tornado 2.2 Problems"
As of 1 April, 2002 (Tornado 2.2 Beta), the Intel Architecture stack
trace library, trcLib, has not been updated to handle subroutine
prologue code which might be inserted for SSE instruction support.
If the Tornado 2.2 compiler is used to build code implementing
Streaming SIMD Extension (SSE or SSE2) instructions, then the -msse
compiler flag may be used so that SSE stack operands are aligned on
the proper boundaries.  The compiler currently supports the alignment
of stack variables by inserting subroutine prologue code that the
stack trace library does not recognize.  An immediate consequence of
this is that routines such as tt() may generate exceptions when one
attempts to trace code that has been built with -msse.


.SS "Validation Test Suite (VTS) Failures"

nvRam test: The first test in this suite may fail on the first attempt 
with a new boot disk.  (NV-RAM is implemented as a file, created on the 
boot disk on the first write command to NV-RAM.)  Subsequent times 
through the test suite should succeed.


Catastrophic error test: fails as the VTS expects
an exception message but this BSP displays none;
however, the BSP correctly recovers
by rebooting the target.

bootline Test:
Bus error test for local error address fails.
Bus error test for off-board error address fails.
Boot commands test failed as the VTS incorrectly presumes a big
endian architecture.


.SH "OTHER"
The valid auxiliary clock rates are between 2 ticks per 
second and 2 to the power of 13 ticks per second (2^13 = 8192).

Warm booting (reboot) is dependent upon the following parameters (shown with
default values) in config.h:

.CS
#define SYS_WARM_BIOS       0   /* warm start from BIOS */
#define SYS_WARM_FD         1   /* warm start from FD */
#define SYS_WARM_ATA        2   /* warm start from ATA */
#define SYS_WARM_TFFS       3   /* warm start from DiskOnChip */

#define SYS_WARM_TYPE       SYS_WARM_FD /* warm start device */
#define SYS_WARM_FD_DRIVE   0   /* 0 = drive a:, 1 = b: */
#define SYS_WARM_FD_TYPE    0   /* 0 = 3.5" 2HD, 1 = 5.25" 2HD */
#define SYS_WARM_ATA_CTRL   0   /* controller 0 */
#define SYS_WARM_ATA_DRIVE  0   /* 0 = c:, 1 = d: */
.CE

If SCSI configuration fails, it may be the result of improper SCSI bus 
termination. Check termination carefully on all devices, including
the controller. Note that some devices
have built in termination that is configured via a jumper.

In order to dynamically update the MMU table entries, prior to MMU
initialization, several dummy entries have been added to the end of the
memory description table sysPhysMemDesc. This allows PCI device
configuration space, configured by the BIOS, to be properly mapped into
the VxWorks memory map. This is done by sysMmuMapAdd() in sysLib.c.

This BSP does not support ISA PnP. Such devices can be supported if
PnP is disabled and the device parameters (IO address, Memory address,
IRQ, DMA channel etc) is set to match its BSP driver configuration. If
the device uses soft-configuration instead of jumpers, an appropriate
utility program, usually available from the device manufacturer,
should be used to setup the device parameters.

DMA Buffer Alignment and cacheLib

If you write device drivers that use Intel 8237 direct memory access 
into buffers obtained from cacheLib, the buffers must be aligned on 
a 64KB boundary and be in the lower memory.

.SS "P5 (Pentium), P6 (PentiumPro, II, III), and P7 (Pentium4) family processor"
Following features are supported for P5 (Pentium), P6 (PentiumPro, II, III), 
and P7 (Pentium4) family processor, and they are enabled in sysHwInit() depending 
upon the feature flags obtained by the CPUID instruction.  
See pentiumLib for more details of these features.

.IP "Memory Type Range Registers (MTRRs)" 
If INCLUDE_MTRR_GET is defined, contents of the MTRRS are copied to the 
sysMtrr[] table.  Otherwise it sets the contents of sysMtrr[] to the MTRRs.

.IP "Performance Monitoring Counter (PMC)"
This is an optional feature configured by INCLUDE_PMC macro.  In this release,
Pentium4's PMC is not supported yet.

.IP "Machine Check Architecture (MCA)"
This is enabled in pentiumMcaEnable() in sysHwInit() if the MCA is supported
by the processor.

.IP "Time Stamp Counter (TSC)"
If INCLUDE_TIMESTAMP_TSC is defined, on-chip TSC is used for the 
time stamp driver.  PENTIUM_TSC_FREQ specifies its frequency.
If it is defined to zero, the frequency is automatically detected.

.IP "Enhanced MMU"
The enhanced MMU is included by defining INCLUDE_MMU_P6_32BIT or
INCLUDE_MMU_P6_36BIT macro.  With INCLUDE_MMU_P6_32BIT, 4KB-page 
and 4MB-page are supported.  With INCLUDE_MMU_P6_36BIT, 4KB-page 
and 2MB-page are supported.  The page size is configurable by 
VM_PAGE_SIZE macro.  Two architecture specific VM library APIs
are provided and linked in automatically.  For bundled VM library,
they are vmBaseArch32Map() and vmBaseArch32Translate().
For unbundled VM library VxVMI, they are vmArch32Map() and 
vmArch32Translate().  Their 36 bit version are also available.
Two new memory attribute macros, VM_STATE_WBACK and 
VM_STATE_GLOBAL, are added.  
VM_STATE_WBACK (clear PWT bit) and VM_STATE_WBACK_NOT (set PWT bit)
represents the cache mode of a page.
VM_STATE_GLOBAL (set GLOBAL bit) and VM_STATE_GLOBAL_NOT (clear
GLOBAL bit) represents the global characteristics of a page.

.IP "Advanced Programmable Interrupt Controller (APIC)"
Intel P6 (PentiumPro, II, and III) and P7 (Pentium4) family processor's 
APIC/xAPIC is supported in either Virtual Wire Mode (define
VIRTUAL_WIRE_MODE in config.h) or Symmetric IO Mode (define 
SYMMETRIC_IO_MODE in config.h).  If neither of them is defined,
VxWorks uses a mode that is set up by BIOS, which could be Virtual
Wire Mode or PIC Mode.  Only Local APIC/xAPIC is used in Virtual Wire 
Mode, both Local APIC/xAPIC and IO APIC/xAPIC are used in Symmetric IO 
Mode.

.IP "Data Cache Mode"
CACHE_COPYBACK data cache mode is default for Pentium. 
It uses Write Back data cache mode with the generic MMU library
for X86 architecture.
CACHE_COPYBACK and CACHE_SNOOP_ENABLE is default for P6 (PentiumPro,
II, III) and P7 (Pentium4) family processors.
CACHE_COPYBACK has no effect to the MMU library with 
INCLUDE_MMU_PENTIUMPRO defined, that support page basis 
Write Back/Write Through cache mode.
CACHE_SNOOP_ENABLE respects MESI cache protocol and doesn't invoke
the WBINVD (write back and invalidate cache) instruction in the
flush routine in the cache library.

.SS "MTRR"
This table shows effective memory type depending on MTRR, PCD, and
PWT setting.

.TS E
expand;
c c c c
c c c c
l l l l.
MTRR mem type	PCD value	PWT value	Effective mem type
_
UC	X	X	UC
WC	0	0	WC
	0	1	WC
	1	0	WC
	1	1	UC
WT	0	X	WT
	1	X	UC
WP	0	0	WP
	0	1	WP
	1	0	UC
	1	1	UC
WB	0	0	WB
	0	1	WT
	1	X	UC
_
.TE

This table shows MTRR memory types and their properties.

.TS E
expand;
c c c c c
c c c c c
l l l l l.
	Cacheable in		Allows	Memory
	L1 and L2	Writeback	Speculative	Ordering
Mnemonic	Caches	Cacheable	Reads	Model
_
UC	No	No	No	Strong Ordering
WC	No	No	Yes	Weak Ordering
WT	Yes	No	Yes	Speculative
				Processor Ordering
WP	Yes for reads,	No	Yes	Speculative
	No for writes			Processor Ordering
WB	Yes	Yes	Yes	Speculative
				Processor Ordering
_
.TE

.SS "DEBUGGING NULL ACCESSES with the MMU"

The macro _WRS_BSP_DEBUG_NULL_ACCESS may be defined in config.h to debug 
NULL accesses in code.  Marking the lower page of RAM invalid in the MMU 
causes any code access to NULL (or any offset from NULL up to page size) 
to throw an exception, suspending the offending task.  Making it very easy 
to debug the NULL access with lkAddr(), and l() from the shell.

Consider this simple errant code which reads from a NULL pointer:

.CS
/* tmp.c */

#include "vxWorks.h"

UINT32 tmpFunc
    (
    void
    )
    {
    UINT32 * badPointer = NULL; /* force a NULL pointer */
    UINT32 tmpValue;

    tmpValue = *badPointer; /* read from the NULL pointer */

    return (tmpValue);
    }
/* end tmp.c */
.CE

Note that this code compiles without error or warning reported.
Execute the errant code on a default vxWorks image.  Note that 
errors are not reported for NULL accesses:

.CS
-> ld < ~/tmp.o
value = 67103608 = 0x3ffeb78 = tmpFunc + 0x1c8
-> tmpFunc
value = 1602816 = 0x187500 = open + 0x1f0
-> *0x0
0x0: value = 1602816 = 0x187500 = open + 0x1f0
-> sp (tmpFunc)
->
.CE

Load the same code to the shell of a target built with the macro
_WRS_BSP_DEBUG_NULL_ACCESS defined. Note that in this case, a page 
fault catches the NULL access.   It also shows which instruction 
caused the access fault, and what access address caused the fault.
Also reported is the processor specific information stating which 
kind of fault occurred.

.CS
-> ld < tmp.o
value = 67103608 = 0x3ffeb78 = tmpFunc + 0x1c8
-> sp (tmpFunc)
task spawned: id = 0x3f3b648, name = t1
value = 66303560 = 0x3f3b648
->
Page Fault
Page Dir Base   : 0x03fd6000
Esp0 0x03f3b618 : 0x00000000, 0x001265ec, 0x00000000, 0x00000000
Esp0 0x03f3b628 : 0x00000000, 0x00000000, 0x00000000, 0x00000000
Program Counter : 0x03ffe9b3
Code Selector   : 0x00000008
Eflags Register : 0x00010246
Error Code      : 0x00000000
Page Fault Addr : 0x00000000
Task: 0x3f3b648 "t1"
.CE

Use the lkAddr() shell command passing the program counter value 
to find the nearest global symbol entry point.

.CS
-> lkAddr (0x03ffe9b3)
0x03ffe9b0 tmpFunc                   text
value = 0 = 0x0
.CE

Use l() on that address to list the errant functions code.

.CS
-> l 0x03ffe9b0

tmpFunc:
0x03ffe9b0  55                      PUSH           EBP
0x03ffe9b1  89 e5                   MOV            EBP, ESP
0x03ffe9b3  a1 00 00 00 00          MOV            0x0, EAX  <-Boom!
0x03ffe9b8  89 ec                   MOV            ESP, EBP
0x03ffe9ba  5d                      POP            EBP
0x03ffe9bb  c3                      RET
= 67103168 = 0x3ffe9c0 = tmpFunc + 0x10
->
.CE

Note that "<-Boom!" shows the instruction which causes an access 
to NULL.  Using this technique, we caught a common error that otherwise
would have gone unseen in execution or in compilation.  A read from NULL 
is one bad thing, but this will also catch the other dangerous case of 
a software write to NULL, for example:

.CS
-> (*(0x0)) = 1

Page Fault
Page Dir Base   : 0x03fd6000
Esp0 0x03f3dd84 :